MC908GR32AVFAE Datasheet, PDF (197/314 Pages) Freescale Semiconductor, Inc – Microcontrollers

Low-Power Modes
14.6.1 Wait Mode
In wait mode, the CPU clocks are inactive while the peripheral clocks continue to run. Figure 14-16 shows
the timing for wait mode entry.
A module that is active during wait mode can wakeup the CPU with an interrupt if the interrupt is enabled.
Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred.
In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the
module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode.
Wait mode also can be exited by a reset or break. A break interrupt during wait mode sets the SIM break
stop/wait bit, SBSW, in the SIM break status register (BSR). If the COP disable bit, COPD, in the
CONFIG1 register is 0, then the computer operating properly module (COP) is enabled and remains
active in wait mode.
IAB
WAIT ADDR
WAIT ADDR + 1
SAME
SAME
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
Note: Previous data can be operand data or the WAIT opcode, depending on the
last instruction.
Figure 14-16. Wait Mode Entry Timing
Figure 14-17 and Figure 14-18 show the timing for WAIT recovery.
IAB
$6E0B
$6E0C $00FF $00FE $00FD $00FC
IDB $A6 $A6
$A6
$01
$0B
$6E
EXITSTOPWAIT
Note: EXITSTOPWAIT = RST pin, CPU interrupt, or break interrupt
Figure 14-17. Wait Recovery from Interrupt or Break
IAB
$6E0B
32
CYCLES
32
CYCLES
RSTVCTH RSTVCTL
IDB $A6 $A6
$A6
RST
CGMXCLK
Figure 14-18. Wait Recovery from Internal Reset
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
Freescale Semiconductor
197