MC908GR32AVFAE Datasheet, PDF (213/314 Pages) Freescale Semiconductor, Inc – Microcontrollers

Interrupts
In a slave SPI (MSTR = 0), MODF generates an SPI receiver/error CPU interrupt request if the ERRIE bit
is set. The MODF bit does not clear the SPE bit or reset the SPI in any way. Software can abort the SPI
transmission by clearing the SPE bit of the slave.
NOTE
A high on the SS pin of a slave SPI puts the MISO pin in a high impedance
state. Also, the slave SPI ignores all incoming SPSCK clocks, even if it was
already in the middle of a transmission.
To clear the MODF flag, read the SPSCR with the MODF bit set and then write to the SPCR register. This
entire clearing mechanism must occur with no MODF condition existing or else the flag is not cleared.
15.7 Interrupts
Four SPI status flags can be enabled to generate CPU interrupt requests. See Table 15-1.
Table 15-1. SPI Interrupts
Flag
SPTE
Transmitter empty
SPRF
Receiver full
OVRF
Overflow
MODF
Mode fault
Request
SPI transmitter CPU interrupt request
(SPTIE = 1, SPE = 1)
SPI receiver CPU interrupt request
(SPRIE = 1)
SPI receiver/error interrupt request
(ERRIE = 1)
SPI receiver/error interrupt request
(ERRIE = 1)
Reading the SPI status and control register with SPRF set and then reading the receive data register
clears SPRF. The clearing mechanism for the SPTE flag is always just a write to the transmit data register.
The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag to generate transmitter CPU
interrupt requests, provided that the SPI is enabled (SPE = 1).
The SPI receiver interrupt enable bit (SPRIE) enables SPRF to generate receiver CPU interrupt requests,
regardless of the state of SPE. See Figure 15-12.
SPTE SPTIE _SPE
SPRIE SPRF
SPI TRANSMITTER
CPU INTERRUPT REQUEST
ERRIE
MODF
OVRF
SPI RECEIVER/ERROR
CPU INTERRUPT REQUEST
Figure 15-12. SPI Interrupt Request Generation
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
Freescale Semiconductor
213