MC908GR32AVFAE Datasheet, PDF (198/314 Pages) Freescale Semiconductor, Inc – Microcontrollers

System Integration Module (SIM)
14.6.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a
module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset also causes an exit from stop mode.
The SIM disables the clock generator module outputs (CGMOUT and CGMXCLK) in stop mode, stopping
the CPU and peripherals. Stop recovery time is selectable using the SSREC bit in CONFIG1. If SSREC
is set, stop recovery is reduced from the normal delay of 4096 CGMXCLK cycles down to 32. This is ideal
for applications using canned oscillators that do not require long startup times from stop mode.
NOTE
External crystal applications should use the full stop recovery time by
clearing the SSREC bit unless OSCENINSTOP bit is set in CONFIG2.
The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop
recovery. It is then used to time the recovery period. Figure 14-19 shows stop mode entry timing. Figure
14-20 shows stop mode recovery time from interrupt.
NOTE
To minimize stop current, all pins configured as inputs should be driven to
a 1 or 0.
CPUSTOP
IAB
STOP ADDR
STOP ADDR + 1
SAME
SAME
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
Note: Previous data can be operand data or the STOP opcode, depending on the last instruction.
Figure 14-19. Stop Mode Entry Timing
CGMXCLK
INT/BREAK
IAB
STOP RECOVERY PERIOD
STOP +1
STOP + 2 STOP + 2
SP
SP – 1
SP – 2
SP – 3
Figure 14-20. Stop Mode Recovery from Interrupt
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
198
Freescale Semiconductor