MC908GR32AVFAE Datasheet, PDF (150/314 Pages) Freescale Semiconductor, Inc – Microcontrollers

Input/Output (I/O) Ports
12.9.2 Data Direction Register G
Data direction register G (DDRG) determines whether each port G pin is an input or an output. Writing a 1
to a DDRG bit enables the output buffer for the corresponding port G pin; a 0 disables the output buffer.
Address:
Read:
Write:
Reset:
$0445
Bit 7
6
5
4
3
2
1
DDRG7 DDRG6 DDRG5 DDRG4 DDRG3 DDRG2 DDRG1
0
0
0
0
0
0
0
Figure 12-24. Data Direction Register G (DDRG)
Bit 0
DDRG0
0
DDRG7–DDRG0 — Data Direction Register G Bits
These read/write bits control port G data direction. Reset clears DDRG7–DDRG0], configuring all port
G pins as inputs.
1 = Corresponding port G pin configured as output
0 = Corresponding port G pin configured as input
NOTE
Avoid glitches on port G pins by writing to the port G data register before
changing data direction register G bits from 0 to 1.
Figure 12-25 shows the port G I/O logic.
READ DDRG ($0445)
WRITE DDRG ($0445)
RESET
WRITE PTG ($0441)
DDRGx
PTGx
PTGx
READ PTG ($0441)
Figure 12-25. Port G I/O Circuit
When bit DDRGx is a 1, reading address $0441 reads the PTGx data latch. When bit DDRGx is a 0,
reading address $0441 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 12-8 summarizes the operation of the port G pins.
Table 12-8. Port G Pin Functions
DDRG
Bit
0
1
PTG
Bit
X⁽¹⁾
X
I/O Pin
Mode
Input, Hi-Z⁽²⁾
Output
Accesses to DDRG
Read/Write
DDRG7–DDRG0
DDRG7–DDRG0
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
Accesses to PTG
Read
Write
Pin
PTG7–PTG0⁽³⁾
PTG7–PTG0
PTG7–PTG0
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
150
Freescale Semiconductor