MC908GR32AVFAE Datasheet, PDF (199/314 Pages) Freescale Semiconductor, Inc – Microcontrollers

SIM Registers
14.7 SIM Registers
The SIM has three memory-mapped registers. Table 14-4 shows the mapping of these registers.
Table 14-4. SIM Registers
Address
$FE00
$FE01
$FE03
Register
BSR
SRSR
BFCR
Access Mode
User
User
User
14.7.1 Break Status Register
The break status register (BSR) contains a flag to indicate that a break caused an exit from wait mode.
This register is only used in emulation mode.
Address: $FE00
Bit 7
6
5
4
3
2
1
Bit 0
Read:
SBSW
R
Write:
R
R
R
R
R
Note⁽¹⁾
R
Reset: 0
0
0
0
0
0
0
0
R
= Reserved
1. Writing a 0 clears SBSW.
Figure 14-21. Break Status Register (BSR)
SBSW — SIM Break Stop/Wait
SBSW can be read within the break state SWI routine. The user can modify the return address on the
stack by subtracting one from it.
1 = Wait mode was exited by break interrupt.
0 = Wait mode was not exited by break interrupt.
14.7.2 SIM Reset Status Register
This register contains six flags that show the source of the last reset provided all previous reset status bits
have been cleared. Clear the SIM reset status register by reading it. A power-on reset sets the POR bit
and clears all other bits in the register.
The register is initialized on power up with the POR bit set and all other bits cleared. During a POR or any
other internal reset, the RST pin is pulled low. After the pin is released, it will be sampled 32 CGMXCLK
cycles later. If the pin is not above V_IH at this time, then the PIN bit may be set, in addition to whatever
other bits are set.
Address: $FE01
Bit 7
6
5
4
3
2
1
Bit 0
Read: POR
PIN
COP
ILOP
ILAD MODRST LVI
0
Write:
Reset: 1
0
0
0
0
0
0
0
= Unimplemented
Figure 14-22. SIM Reset Status Register (SRSR)
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
Freescale Semiconductor
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