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MC908GR32AVFAE Datasheet, PDF (257/314 Pages) Freescale Semiconductor, Inc – Microcontrollers
I/O Registers
Table 18-2. Mode, Edge, and Level Selection
MSxB
X
X
0
0
0
0
0
0
0
1
1
1
MSxA
0
1
0
0
0
1
1
1
1
X
X
X
ELSxB
0
0
0
1
1
0
0
1
1
0
1
1
ELSxA
0
0
1
0
1
0
1
0
1
1
0
1
Mode
Configuration
Output preset
Pin under port control;
initial output level high
Pin under port control;
initial output level low
Capture on rising edge only
Input capture
Capture on falling edge only
Capture on rising
or falling edge
Software compare only
Output compare Toggle output on compare
or PWM
Clear output on compare
Set output on compare
Buffered
output
compare or
buffered PWM
Toggle output on compare
Clear output on compare
Set output on compare
ELSxB and ELSxA — Edge/Level Select Bits
When channel x is an input capture channel, these read/write bits control the active edge-sensing logic
on channel x.
When channel x is an output compare channel, ELSxB and ELSxA control the channel x output
behavior when an output compare occurs.
When ELSxB and ELSxA are both clear, channel x is not connected to port D or port F, and pin
PTDx/T2CHx or pin PTFx/T2CHx is available as a general- purpose I/O pin. Table 18-2 shows how
ELSxB and ELSxA work. Reset clears the ELSxB and ELSxA bits.
NOTE
After initially enabling a TIM2 channel register for input capture operation
and selecting the edge sensitivity, clear CHxF to ignore any erroneous
edge detection flags.
TOVx — Toggle-On-Overflow Bit
When channel x is an output compare channel, this read/write bit controls the behavior of the channel
x output when the TIM2 counter overflows. When channel x is an input capture channel, TOVx has no
effect. Reset clears the TOVx bit.
1 = Channel x pin toggles on TIM2 counter overflow.
0 = Channel x pin does not toggle on TIM2 counter overflow.
NOTE
When TOVx is set, a TIM2 counter overflow takes precedence over a
channel x output compare if both occur at the same time.
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
Freescale Semiconductor
257