MC908GR32AVFAE Datasheet, PDF (229/314 Pages) Freescale Semiconductor, Inc – Microcontrollers

Functional Description
17.3.3 Output Compare
With the output compare function, the TIM1 can generate a periodic pulse with a programmable polarity,
duration, and frequency. When the counter reaches the value in the registers of an output compare
channel, the TIM1 can set, clear, or toggle the channel pin. Output compares can generate TIM1 CPU
interrupt requests.
17.3.3.1 Unbuffered Output Compare
Any output compare channel can generate unbuffered output compare pulses as described in 17.3.3
Output Compare. The pulses are unbuffered because changing the output compare value requires writing
the new value over the old value currently in the TIM1 channel registers.
An unsynchronized write to the TIM1 channel registers to change an output compare value could cause
incorrect operation for up to two counter overflow periods. For example, writing a new value before the
counter reaches the old value but after the counter reaches the new value prevents any compare during
that counter overflow period. Also, using a TIM1 overflow interrupt routine to write a new, smaller output
compare value may cause the compare to be missed. The TIM1 may pass the new value before it is
written.
Use the following methods to synchronize unbuffered changes in the output compare value on channel x:
• When changing to a smaller value, enable channel x output compare interrupts and write the new
value in the output compare interrupt routine. The output compare interrupt occurs at the end of
the current output compare pulse. The interrupt routine has until the end of the counter overflow
period to write the new value.
• When changing to a larger output compare value, enable TIM1 overflow interrupts and write the
new value in the TIM1 overflow interrupt routine. The TIM1 overflow interrupt occurs at the end of
the current counter overflow period. Writing a larger value in an output compare interrupt routine
(at the end of the current pulse) could cause two output compares to occur in the same counter
overflow period.
17.3.3.2 Buffered Output Compare
Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the
T1CH0 pin. The TIM1 channel registers of the linked pair alternately control the output.
Setting the MS0B bit in TIM1 channel 0 status and control register (TSC0) links channel 0 and channel 1.
The output compare value in the TIM1 channel 0 registers initially controls the output on the T1CH0 pin.
Writing to the TIM1 channel 1 registers enables the TIM1 channel 1 registers to synchronously control the
output after the TIM1 overflows. At each subsequent overflow, the TIM1 channel registers (0 or 1) that
control the output are the ones written to last. T1SC0 controls and monitors the buffered output compare
function, and TIM1 channel 1 status and control register (T1SC1) is unused. While the MS0B bit is set,
the channel 1 pin, T1CH1, is available as a general-purpose I/O pin.
NOTE
In buffered output compare operation, do not write new output compare
values to the currently active channel registers. User software should track
the currently active channel to prevent writing a new value to the active
channel. Writing to the active channel registers is the same as generating
unbuffered output compares.
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
Freescale Semiconductor
229