MC908GR32AVFAE Datasheet, PDF (191/314 Pages) Freescale Semiconductor, Inc – Microcontrollers

Exception Control
14.5.1.1 Hardware Interrupts
A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after
completion of the current instruction. When the current instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I bit clear in the condition code register) and if the
corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.
MODULE
INTERRUPT
I BIT
IAB
IDB
R/W
DUMMY
SP
SP – 1 SP – 2 SP – 3 SP – 4 VECT H VECT L START ADDR
DUMMY PC – 1[7:0] PC – 1[15:8] X
A
CCR V DATA H V DATA L OPCODE
Figure 14-8. Interrupt Entry Timing
MODULE
INTERRUPT
I BIT
IAB
IDB
R/W
SP – 4 SP – 3 SP – 2 SP – 1
SP
PC
PC + 1
CCR
A
X PC – 1 [7:0] PC – 1 [15:8] OPCODE OPERAND
Figure 14-9. Interrupt Recovery Timing
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
Freescale Semiconductor
191