MC908GR32AVFAE Datasheet, PDF (239/314 Pages) Freescale Semiconductor, Inc – Microcontrollers

Input/Output Registers
NOTE
When TOVx is set, a TIM1 counter overflow takes precedence over a
channel x output compare if both occur at the same time.
CHxMAX — Channel x Maximum Duty Cycle Bit
When the TOVx bit is at 1, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered
PWM signals to 100%. As Figure 17-9 shows, the CHxMAX bit takes effect in the cycle after it is set
or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared.
NOTE
The 100% PWM duty cycle is defined as a continuous high level if the PWM
polarity is 1 and a continuous low level if the PWM polarity is 0. Conversely,
a 0% PWM duty cycle is defined as a continuous low level if the PWM
polarity is 1 and a continuous high level if the PWM polarity is 0.
OVERFLOW
OVERFLOW
PERIOD
OVERFLOW
OVERFLOW
OVERFLOW
TCHx
CHxMAX
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 17-9. CHxMAX Latency
17.8.5 TIM1 Channel Registers
These read/write registers contain the captured TIM1 counter value of the input capture function or the
output compare value of the output compare function. The state of the TIM1 channel registers after reset
is unknown.
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM1 channel x registers
(T1CHxH) inhibits input captures until the low byte (T1CHxL) is read.
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of the TIM1 channel x registers
(T1CHxH) inhibits output compares until the low byte (T1CHxL) is written.
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
Freescale Semiconductor
239