CC2510FX Datasheet, PDF (99/253 Pages) List of Unclassifed Manufacturers – True System-on-Chip with Low Power RF Transceiver and 8051 MCU

CC2510Fx / CC2511Fx
Figure 17 : Up/down mode
13.3.6 Channel Mode Control
The channel mode is set with each channel’s
control and status register T1CCTLn. The
settings include input capture and output
compare modes.
13.3.7 Input Capture Mode
When a channel is configured as an input
capture channel, the I/O pin associated with
that channel, is configured as an input. After
the timer has been started, a rising edge,
falling edge or any edge on the input pin will
trigger a capture of the 16-bit counter contents
into the associated capture register. Thus the
timer is able to capture the time when an
external event takes place.
Note: before an I/O pin can be used by the
timer, the required I/O pin must be configured
as a Timer 1 peripheral pin as described in
section 13.1.4 on page 67 .
The channel input pin is synchronized to the
internal system clock. Thus pulses on the input
pin must have a minimum duration greater
than the system clock period.
The content of the 16-bit capture register is
read out from registers T1CCnH:T1CCnL.
When the capture takes place the interrupt flag
for the channel is set. This bit is
T1CTL.CH0IF for channel 0, T1CTL.CH1IF
for channel 1, and T1CTL.CH2IF for channel
2. An interrupt request is generated if the
corresponding interrupt mask bit on
T1CCTL0.IM, T1CCTL1.IM, or T1CCTL2.IM,
respectively, is set.
capture. This function is selected with the
register bit T1CCTLx.CPSEL which selects to
use either the input pin or the RFIF interrupt as
capture event. When RFIF is selected as
capture input, the interrupt source(s) enabled
by RFIM (see section 15.3.1 on page 193) will
trigger a capture. In this way the timer can be
used to capture a value when e.g. a start of
frame delimiter (SFD) is detected.
13.3.8 Output Compare Mode
In output compare mode the I/O pin associated
with a channel is set as an output. After the
timer has been started, the contents of the
counter is compared with the contents of the
channel compare register T1CCnH:T1CCnL. If
the compare register equals the counter
contents, the output pin is set, reset or toggled
according to the compare output mode setting
of T1CCTLn.CMP. Note that all edges on
output pins are glitch-free when operating in a
given output compare mode. Writing to the
compare register T1CCnL is buffered so that a
value written to T1CCnL does not take effect
until the corresponding high order register,
T1CCnH is written. For output compare modes
1-3, a new value written to the compare
register T1CCnH:T1CCnL takes effect after the
registers have been written. For other output
compare modes the new value written to the
compare register take effect when the timer
reaches 0x0000.
Note that channel 0 has fewer output compare
modes than channel 1 and 2 because
T1CC0H:T1CC0L has a special function in
modes 6 and 7, meaning these modes would
not be useful for channel 0.
13.3.7.1 RF Event Capture
Each timer channel may be configured so that
an RF interrupt RFIF event will trigger a
capture instead of the normal input pin
When a compare occurs, the interrupt flag for
the channel is set. This bit is T1CTL.CH0IF
for channel 0, T1CTL.CH1IF for channel 1,
and T1CTL.CH2IF for channel 2. An interrupt
request is generated if the corresponding
CC2510Fx/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A Page 99 of 252