CC2510FX Datasheet, PDF (181/253 Pages) List of Unclassifed Manufacturers – True System-on-Chip with Low Power RF Transceiver and 8051 MCU

CC2510Fx / CC2511Fx
0xDE13: USBMAXO – Max. packet size for OUT endpoint
Bit Field Name
Reset
R/W Description
7:0 USBMAXO[7:0]
0x00
R/W Maximum packet size in units of 8 bytes for OUT
endpoint selected by USBINDEX register. The value
of this register should correspond to the
wMaxPacketSize field in the Standard Endpoint
Descriptor for the endpoint. This register must not be
set to a value grater than the available FIFO memory
for the endpoint.
0xDE14: USBCSOL – OUT EP{1-5} Control and Status Low
Bit Field Name
Reset
R/W Description
7 CLR_DATA_TOG
6 SENT_STALL
5 SEND_STALL
4 FLUSH_PACKET
3 DATA_ERROR
2 OVERRUN
1 FIFO_FULL
0 OUTPKT_RDY
0
R/W Setting this bit will reset the data toggle to 0. Thus,
setting this bit will force the next data packet to be a
H0 _{DATA0 packet. This bit is automatically cleared.}
0
R/W This bit is set when a STALL has been sent. This bit
must be cleared from firmware.
0
R/W Set this bit to make the USB Controller reply with a
STALL handshake. Firmware must clear this bit to
end the stall condition. It is not possible to stall an
isochronous endpoint, thus this bit will only have
effect if the OUT endpoint is configured as
bulk/interrupt.
0
R/W Flush next packet that is to be read from the OUT
FIFO. If there are two packets in the IN FIFO due to
H0 _{double buffering, this bit must be set twice to}
completely flush the IN FIFO. This bit is
automatically cleared.
0
R
This bit is set if there is a CRC or bit-stuff error in the
packet received. Cleared when OUTPKT_RDY is
cleared. This bit will only be valid if the OUT endpoint
type is isochronous. Bulk/Interrupt endpoints use
retransmission when errors occur while there is no
retransmission for isochronous endpoints.
0
R/W This bit is set when an OUT packet cannot be loaded
into the OUT FIFO and the OUT endpoint type is
isochronous. Firmware should clear this bit.
0
R OUT FIFO full. No more packets can be loaded.
0
R/W This bit is set when a packet has been successfully
received and is ready to be read from OUT FIFO.
This bit should be cleared as soon as the packet has
been unloaded from the FIFO. The interrupt flag for
the OUT endpoint is set when this bit is set.
CC2510Fx/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A Page 181 of
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