CC2510FX Datasheet, PDF (167/253 Pages) List of Unclassifed Manufacturers – True System-on-Chip with Low Power RF Transceiver and 8051 MCU

CC2510Fx / CC2511Fx
13.15.1 USB Registers
The operation of the USB is configured
through a set of USB registers. These
USB registers are mapped to XDATA
memory space as shown in Figure 10 on
page 36.
In addition to configuration registers, the
USB registers also provide status
information.
The USB registers control/status bits are
referred to where appropriate in the
following sections while section 13.15.11
on page 175 gives a full description of all
USB registers.
13.15.2 48 MHz Clock
A 48 MHz external crystal must be used
for the USB Controller to operate correctly.
This 48 MHz clock is divided by two
internally to generate the system clock at
24 MHz. It is important that the crystal
oscillator is stable before the USB
Controller is accessed. See 13.10.3 for
details on how to set up the crystal
oscillator.
13.15.3 USB Enable
The USB Controller must be enabled
before it is used. This is performed by
setting the SLEEP.USB_EN bit to 1.
Setting SLEEP.USB_EN to 0 will reset the
USB Controller.
13.15.4 USB Interrupts
There are 3 interrupt flag registers with
associated interrupt enable mask
registers. The USBCIF register contains
flags for common USB interrupts. The
USBIIF register has interrupt flags for
endpoint 0 and all the IN endpoints.
USBOIF has interrupt flags for all OUT
endpoints. All interrupts except SOF and
and SUSPEND are initially enabled after
reset.
When the interrupt flag of an enabled
interrupt is set, the USB interrupt is
asserted. This interrupts the 8051 CPU
which will start executing the interrupt
service routine if there is no higher priority
interrupts pending. The USB Controller
uses interrupt number 6 for USB
interrupts. This is the same interrupt
number used for Port 2 inputs. Thus, the
interrupt routine must also handle Port 2
interrupts if they are used. The interrupt
routine should read all the interrupt flag
registers and take action depending on the
status of the flags. The interrupt flag
registers will be cleared when they are
read. The interrupt flags must therefore be
saved in memory (typically in a local
variable on the stack) to be used in
multiple operations.
To enable USB interrupts IEN2.P2IE
must be set to 1. It is important that the
P2IFG register is cleared and then the
IRCON2.P2IF bit is cleared at the end of
the USB interrupt service routine after the
interrupt flags have been read. This allows
new USB/P2 interrupts to be detected.
Refer to Table 33 for a complete list of
interrupts and section 12.7 for more details
about interrupts.
13.15.4.1 USB Resume Interrupt
Bit 7 of Port 0 is used to wake up the
CC2511Fx from PM1/suspend when resume
signaling has been detected on the USB
bus. IEN1.P0IE must therefore be set to
1 to enable P0 interrupts. PICTL.P0IENH
must be set to 1 to enable interrupts on
P0[7:4] and PICTL.P0ICON must be 0 to
enable interrupts on rising edge. The P0
interrupt routine should check bit 7 of
P0IFG and resume if this bit is set. Notice
that bit 7 and bit 6 of Port 0 are not
available as external ports on CC2511Fx. If
PM1 is entered from within an interrupt
routine (typically the USB/P2 interrupt
routine) due to a suspend interrupt, it is
important that the priority of the P0
interrupt is set higher than the interrupt
that entered PM1. See section 13.15.9 for
more details about suspend and resume.
13.15.5 Endpoint 0
Endpoint 0 (EP0) is a bi-directional control
endpoint. A USB function is required to
implement a control endpoint at endpoint
0. During the enumeration phase all
communication is performed across this
endpoint. Before the USBADDR register has
been set (to a value other than 0), the
USB Controller will only be able to
communicate through endpoint 0. Setting
the USBADDR register will bring the USB
function out of the Default state in the
enumeration phase and into the
CC2510Fx/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A Page 167 of
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