CC2510FX Datasheet, PDF (69/253 Pages) List of Unclassifed Manufacturers – True System-on-Chip with Low Power RF Transceiver and 8051 MCU

CC2510Fx / CC2511Fx
locations. Note that if both USARTs are used,
they must be on different ports, i.e. one on P0
and one on P1. This applies both in UART and
SPI mode.
In Table 41, the USART1 signals are shown as
follows:
• RX : RXDATA
• TX : TXDATA
SPI:
• MI : MISO
• MO : MOSI
• C : SCK
• SS : SSN
P2DIR.PRIP0 selects the order of
precedence when assigning several
peripherals to port 0. When set to 01, USART1
has precedence. Note that if UART mode is
selected, USART0 or timer 1 will have
precedence to use ports P0_2 and P0_3.
P2SEL.PRI3P1 and P2SEL.PRI2P1 select
the order of precedence when assigning
several peripherals to port 1. USART1 has
precedence when the former is set to 1 and
the latter is set to 0. Note that if UART mode is
selected, USART0 or timer 3 will have
precedence to use ports P2_4 and P2_5.
13.1.4.3 Timer 1
PERCFG.T1CFG selects whether to use
alternative 1 or alternative 2 locations.
In Table 41, the Timer 1 signals are shown as
the following:
• 0 : Channel 0 capture/compare pin
• 1 : Channel 1 capture/compare pin
• 2 : Channel 2 capture/compare pin
P2DIR.PRIP0 selects the order of
precedence when assigning several
peripherals to port 0. When set to 10 or 11 the
timer 1 channels have precedence.
P2SEL.PRI1P1 and P2SEL.PRI0P1 select
the order of precedence when assigning
several peripherals to port 1. The timer 1
channels have precedence when the former is
set low and the latter is set high.
13.1.4.4 Timer 3
PERCFG.T3CFG selects whether to use
alternative 1 or alternative 2 locations.
In Table 41, the Timer 3 signals are shown as
the following:
• 0 : Channel 0 capture/compare pin
• 1 : Channel 1 capture/compare pin
P2SEL.PRI2P1 selects the order of
precedence when assigning several
peripherals to port 1. The timer 3 channels
have precedence when the bit is set.
13.1.4.5 Timer 4
PERCFG.T4CFG selects whether to use
alternative 1 or alternative 2 locations.
In Table 41, the Timer 4 signals are shown as
the following:
• 0 : Channel 0 capture/compare pin
• 1 : Channel 1 capture/compare pin
P2SEL.PRI1P1 selects the order of
precedence when assigning several
peripherals to port 1. The timer 4 channels
have precedence when the bit is set.
13.1.4.6 I2S
The I2S configuration register bit
I2SCFG1.IOLOC selects whether to use
alternative 1 or alternative 2 locations.
In Table 41, the I2S signals are shown as
follows:
• CK : Continous Serial Clock (SCK)
• WS : Word Select
• RX : Serial Data In
• TX : Serial Data Out
13.1.5 ADC
When using the ADC in an application, the
Port 0 pins used must be configured as ADC
inputs. Up to eight ADC inputs can be used.
The port pins are mapped to the ADC inputs
so that P0_7 – P0_0 corresponds to AIN7-
AIN0. To configure a Port 0 pin to be used as
an ADC input the corresponding bit in the
ADCCFG register must be set to 1. The default
values in this register select the Port 0 pins as
non-ADC input i.e. digital input/outputs. The
settings in the ADCCFG register override the
settings in P0SEL.
CC2510Fx/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A Page 69 of 252