CC2510FX Datasheet, PDF (104/253 Pages) List of Unclassifed Manufacturers – True System-on-Chip with Low Power RF Transceiver and 8051 MCU

CC2510Fx / CC2511Fx
TIMIF.OVFIM. If there are other pending
interrupts, the corresponding interrupt flag
must be cleared by software before a new
interrupt request is generated. Also, enabling
an interrupt mask bit will generate a new
interrupt request if the corresponding interrupt
flag is set.
When the timer is used in Free-running Mode
or Modulo Mode the interrupt flags are set as
follows:
• T1CTL.CH0IF, T1CTL.CH1IF and
T1CTL.CH2IF are set on
compare/capture event
• T1CTL.OVFIF is set when counter
reaches terminal count value
When the timer is used in Up/Down Mode the
interrupt flags are set as follows:
In compare mode:
• T1CTL.CH0IF and T1CTL.OVFIF
are set when counter turns around on
zero
• T1CTL.CH1IF and T1CTL.CH2IF
are set on compare event
In capture mode:
• T1CTL.CH0IF, T1CTL.CH1IF and
T1CTL.CH2IF are set on capture
event
• T1CTL.OVFIF is set when counter
turns around on zero
13.3.10 Timer 1 DMA Triggers
There are three DMA triggers associated with
Timer 1, one for each channel. These are
DMA triggers T1_CH0, T1_CH1 and T1_CH2
which are generated when the corresponding
interrupt flags are set:
• T1_CH0 is generated when
T1CTL.CH0IF is set
• T1_CH1 is generated when
T1CTL.CH0IF is set
• T1_CH2 is generated when
T1CTL.CH0IF is set
See Table 42 for a list of all DMA triggers.
13.3.11 DSM Mode
Timer 1 also contains a 1-bit Delta Sigma
Modulator (DSM) of second order that can be
used to produce a high quality mono audio
output PWM signal. The DSM removes the
need for high order external filtering required
when using regular PWM mode.
The DSM operates at a fixed speed of either
1/4 or 1/8 of the Timer 1 update speed
(CLKCON.TICKSPD) while input samples are
updated at a configurable sampling rate set by
Timer 1 channel 0.
An interpolator is used to match the sampling
rate with the DSM update rate. This
interpolator is of first order with a scaling
compensation. The scaling compensation is
due to variable gain defined by the difference
in sampling speed and DSM speed. This
interpolation mechanism can be disabled, thus
using a zeroth interpolator.
In addition to the interpolator, a shaper can be
used to account for differences in rise/fall
times in the output signal. This shaper ensures
a rising and a falling edge per bit and will thus
limits the output swing to the range 1/8 to 7/8
of I/O VDD when the DSM operates at 1/8 of
the Timer 1 update speed or 1/4 to 3/4 of I/O
VDD when the DSM operates at 1/4 of the
Timer 1 update speed.
The DSM is used as in PWM mode where
channel 0 defines the period/sampling rate.
The DSM can not use the Timer 1 prescaler to
further slow down the period.
CLKCON.TICKSPD, however, can be used.
Timer 1 channel 0 must be configured to
compare modulo mode and have a terminal
count value that matches the incoming sample
rate. Table 44 shows some Timer 1 channel 0
periode settings (T1CC0 register) for different
Timer 1 clock speeds and data rates (note that
tick speed is not used, i.e. CLKCON.TICKSPD
= 000).
CC2510Fx/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A Page 104 of 252