CC2510FX Datasheet, PDF (179/253 Pages) List of Unclassifed Manufacturers – True System-on-Chip with Low Power RF Transceiver and 8051 MCU

CC2510Fx / CC2511Fx
0xDE10: USBMAXI – Max. packet size for IN endpoint
Bit Field Name
Reset
R/W Description
7:0 USBMAXI[7:0]
0x00
R/W Maximum packet size in units of 8 bytes for IN
endpoint selected by USBINDEX register. The value
of this register should correspond to the
wMaxPacketSize field in the Standard Endpoint
Descriptor for the endpoint. This register must not be
set to a value grater than the available FIFO memory
for the endpoint.
0xDE11: USBCS0 – EP0 Control and Status (USBINDEX = 0)
Bit Field Name
Reset
R/W Description
7 CLR_SETUP_END
6 CLR_OUTPKT_RDY
5 SEND_STALL
4 SETUP_END
3 DATA_END
2 SENT_STALL
1 INPKT_RDY
0 OUTPKT_RDY
0
R/W Set this bit to clear the SETUP_END bit. It will be
cleared automatically.
H0
0
R/W Set this bit to clear the OUTPKT_RDY bit. It will be
cleared automatically.
H0
0
R/W Set this bit to make the USB Controller reply with a
STALL during the next transfer. This bit is
H0 _{automatically cleared. Used to terminate the current}
transaction.
0
R
This bit is set if the control transfer ends due to a
premature end of control transfer. The FIFO will be
flushed and the interrupt flag USBIIF.EP0IF will be
set. Set the CLR_SETUP_END bit to clear this bit.
0
R/W This bit is used to signal the end of a data transfer.
This bit must be set in the following three situations:
H0
• When the last data packet has been
loaded and INPKT_RDY is set
• When the last data packet has been
unloaded and CLR_OUTPKT_RDY is set
• When INPKT_RDY is set without having
loaded the FIFO (for sending a zero length
data packet).
The USB Controller will clear this bit automatically.
0
R/W This bit is set when a STALL has been sent. The
interrupt flag USBIIF.EP0 will be set. This bit must be
H1 _{cleared from firmware.}
0
R/W Set this bit when a data packet has been loaded into
the EP0 FIFO to notify the USB Controller that a new
H0 _{data packet is ready to be transferred. When the}
data packet has been sent, this bit is cleared and the
interrupt flag is set.
0
R
Data packet received. This bit is set when an
incoming data packet has been placed in the OUT
FIFO. Set the CLR_OUTPKT_RDY bit to clear this
bit. The interrupt flag is also set when this bit is set.
CC2510Fx/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A Page 179 of
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