CC2510FX Datasheet, PDF (169/253 Pages) List of Unclassifed Manufacturers – True System-on-Chip with Low Power RF Transceiver and 8051 MCU

CC2510Fx / CC2511Fx
3. Set
the
USBCS0.CLR_OUTPKT_RDY bit.
This denotes the end of the Setup
stage. If the control transfer has
no
Data
stage,
the
USBCS0.DATA_END bit must also
be set. If there is no Data stage,
the USB Controller will stay in the
IDLE state.
13.15.5.4 IN Transactions (TX state)
If the control transfer requires data to be
sent to the host, the Setup Stage will be
followed by one or more IN transactions (a
Data IN stage). In this case the USB
Controller will be in TX state and only
accept IN tokens. If more than 32 bytes
(maximum packet size) is to be sent, the
data must be split into a number of 32 byte
packets followed by a residual packet. If
the number of bytes to send is divisible by
32, the residual packet will be a zero
length data packet. Thus, a packet size
less than 32 bytes denotes the end of the
transfer.
Firmware should load the EP0 FIFO with
the first data packet and set the
USBCS0.INPKT_RDY bit as soon as
possible
after
the
USBCS0.CLR_OUTPKT_RDY bit has been
set. The USBCS0.INPKT_RDY bit will be
cleared and an EP0 interrupt will be
generated when the data packet has been
sent. Firmware might then load more data
packets as necessary. An EP0 interrupt
will be generated for each packet sent.
Firmware must set USBCS0.DATA_END in
addition to USBCS0.INPKT_RDY when the
last data packet has been loaded. This will
start the Status stage of the control
transfer.
EP0 will switch to the IDLE state when the
Status stage has completed. The Status
stage
may
fail
if
the
USBCS0.SEND_STALL bit is set. The
USBCS0.SENT_STALL bit will then be set
and an interrupt will be generated as
explained in section 13.15.5.2.
If USBCS0.INPKT_RDY is not set when
receiving an IN token, the USB Controller
will reply with a NAK to indicate that the
endpoint is working, but temporarily has
no data to send.
13.15.5.5 OUT Transactions (RX state)
If the control transfer requires data to be
received from the host, the Setup stage
will be followed by one or more OUT
transactions (a Data OUT stage). In this
case the USB Controller will be in RX state
and only accept OUT tokens. If more than
32 bytes (maximum packet size) is to be
received, the data must be split into a
number of 32 byte packets followed by a
residual packet. If the number of bytes is
divisible by 32, the residual packet will be
a zero length data packet. Thus, a packet
size less than 32 bytes denotes the end of
the transfer.
The USBCS0.OUTPKT_RDY bit will be set
and an EP0 interrupt will be generated
when a data packet has been received.
The
firmware
should
set
USBCS0.CLR_OUTPKT_RDY when the
data packet has been unloaded from the
EP0 FIFO. When the last data packet has
been received (packet size less than 32)
firmware
should
also
set
USBCS0.DATA_END. This will start the
Status stage of the control transfer.
EP0 will switch to the IDLE state when the
Status stage has completed. The Status
stage may fail if the DATA1 packet
received is not a zero length data packet
or the USBCS0.SEND_STALL bit is set.
The USBCS0.SENT_STALL bit will then be
set and an interrupt will be generated as
explained in section 13.15.5.2.
13.15.6 Endpoints 1 – 5
Each endpoint can be used as a IN only,
OUT only or IN/OUT. For a IN/OUT
endpoint there are basically two endpoints,
a IN and a OUT endpoint assiociated with
the endpoint number. Configuration and
control of IN endpoints is performed by
accessing the USBCSIL and USBCSIH
registers. The USBCSOL and USBCSOH
registers are used to configure and control
OUT endpoints. Each IN and OUT
endpoint can be configured as a
Isochronous or Bulk/Interrupt endpoint.
This is done by setting the USBCSIH.ISO
and USBCSOH.ISO bits. Bulk and Interrupt
endpoints are handled identically by the
USB Controller but will have different
properties from a firmware perspective.
CC2510Fx/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A Page 169 of
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