CC2510FX Datasheet, PDF (49/253 Pages) List of Unclassifed Manufacturers – True System-on-Chip with Low Power RF Transceiver and 8051 MCU

CC2510Fx / CC2511Fx
Instruction
CY
OV
AC
ADD
x
x
x
ADDC
x
x
x
SUBB
x
x
x
MUL
0
x
DIV
0
x
DA
x
RRC
x
RLC
x
SETB C
1
CLR C
x
CPL C
x
ANL C,bit
x
ANL C,/bit
x
ORL C,bit
x
ORL C,/bit
x
MOV C,bit
x
CJNE
x
“0”=set to 0, “1”=set to 1, “x”=set to 0/1, “-“=not affected
Table 32: Instructions that affect flag settings
12.7 Interrupts
The CPU has 18 interrupt sources. Each
source has its own request flag located in a set
of Interrupt Flag SFR registers. Each interrupt
requested by the corresponding flag can be
individually enabled or disabled. The
definitions of the interrupt sources and the
interrupt vectors are given in Table 33.
I2S and USART1 share interrupts. On the
CC2511Fx USB shares interrupt with Port 2
inputs. The interrupt aliases for I2S and USB
are listed in Table 34. The original interrupt
names, masks and flags in Table 33, however,
are used in the following sections.
The interrupts are grouped into a set of priority
level groups with selectable priority levels.
The interrupt enable registers are described in
section 12.7.1 and the interrupt priority settings
are described in section 12.7.4 on page 58.
12.7.1 Interrupt Masking
Each interrupt can be individually enabled or
disabled by the interrupt enable bits in the
Interrupt Enable SFRs IEN0, IEN1 and IEN2.
The Interrupt Enable SFRs are described
below and summarized in Table 33.
Note that some peripherals have several
events that can generate the interrupt request
associated with that peripheral. This applies to
Port 0, Port 1, Port 2, DMA, Timer 1, Timer 3 ,
Timer 4 and Radio. These peripherals have
interrupt mask bits for each internal interrupt
source in the corresponding SFR registers.
In order to use any of the interrupts in the
CC2510Fx/CC2511Fx the following steps must be
taken
1. Set the corresponding individual
interrupt enable bit in the IEN0, IEN1
or IEN2 register to 1.
2. Set individual interrupt enable bit in
the peripherals SFR register, if any.
3. Begin the interrupt service routine at
the corresponding vector address of
that interrupt. See Table 33 for
addresses.
4. Enable global interrupt by setting the
EA bit in IEN0 to 1
CC2510Fx/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A Page 49 of 252