CC2510FX Datasheet, PDF (147/253 Pages) List of Unclassifed Manufacturers – True System-on-Chip with Low Power RF Transceiver and 8051 MCU

CC2510Fx / CC2511Fx
13.13 USART
USART0 and USART1 are serial
communications interfaces that can be
operated separately in either
asynchronous UART mode or in
synchronous SPI mode. The two USARTs
have identical function, and are assigned
to separate I/O pins. Refer to section 13.1
for I/O configuration.
13.13.1 UART mode
For asynchronous serial interfaces, the
UART mode is provided. In the UART
mode the interface uses a two-wire
interface consisting of the pins RXD and
TXD. The UART mode of operation
includes the following features:
• 8 or 9 data bits
• Odd, even or no parity
• Configurable start and stop bit level
• Configurable LSB or MSB first transfer
• Independent receive and transmit
interrupts
• Independent receive and transmit
DMA triggers
• Parity and framing error status
The UART mode provides full duplex
asynchronous transfers, and the
synchronization of bits in the receiver does
not interfere with the transmit function. A
UART byte transfer consists of a start bit,
eight data bits, an optional ninth data or
parity bit, and one or two stop bits. Note
that the data transferred is referred to as a
byte, although the data can actually
consist of eight or nine bits.
The UART operation is controlled by the
USART Control and Status registers,
UxCSR and the UART Control register
UxUCR where x is the USART number, 0
or 1.
The UART mode is selected when
UxCSR.MODE is set to 1.
13.13.1.1 UART Transmit
A UART transmission is initiated when the
USART Receive/Transmit Data Buffer,
UxDBUF register is written. The byte is
transmitted on the TXDx output pin. The
UxDBUF register is double-buffered.
The UxCSR.ACTIVE bit goes high when
the byte transmission starts and low when
it ends. When byte transmission ends the
UxCSR.TX_BYTE bit is set. An interrupt
request is generated when the UxDBUF
register is ready to accept new transmit
data. This happens immediately after the
transmission has been started, hence a
new data byte value can be loaded into
the data buffer while a byte is being
transmitted.
13.13.1.2 UART Receive
Data reception on the UART is initiated
when a 1 is written to the UxCSR.RE bit.
The UART will then search for a valid start
bit on the RXDx input pin and set the
UxCSR.ACTIVE bit high. When a valid
start bit has been detected the received
byte is shifted into the receive register.
The UxCSR.RX_BYTE bit is set when the
operation has completed, and a receive
interrupt is generated. At the same time
UxCSR.ACTIVE will go low.
The received data byte is available
through the UxDBUF register. When
UxDBUF is read, UxCSR.RX_BYTE is
cleared by hardware.
13.13.1.3 UART Character Format
If the BIT9 and PARITY bits in register
UxUCR are set high, parity generation and
detection is enabled. The parity is
computed and transmitted as the ninth bit,
and during reception, the parity is
computed and compared to the received
ninth bit. If there is a parity error, the
UxCSR.ERR bit is set high. This bit is
cleared when UxCSR is read.
The number of stop bits to be transmitted
is set to one or two bits determined by the
register bit UxUCR.SPB. The receiver will
always check for one stop bit. If the first
stop bit received during reception is not at
the expected stop bit level, a framing error
is signaled by setting register bit
UxCSR.FE high. UxCSR.FE is cleared
when UxCSR is read. The receiver will
CC2510Fx/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A Page 147 of
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