CC2510FX Datasheet, PDF (84/253 Pages) List of Unclassifed Manufacturers – True System-on-Chip with Low Power RF Transceiver and 8051 MCU

CC2510Fx / CC2511Fx
13.2 DMA Controller
The CC2510Fx/CC2511Fx includes a direct
memory access (DMA) controller, which can
be used to relieve the 8051 CPU core of
handling data movement operations. Thus the
CC2510Fx/CC2511Fx can achieve high overall
performance with good power efficiency. The
DMA controller can move data from a
peripheral unit such as ADC or RF transceiver
to memory with minimum CPU intervention.
The DMA controller module coordinates all
DMA transfers, ensuring that DMA requests
are prioritized appropriately relative to each
other and CPU memory access. The DMA
controller contains a number of programmable
DMA channels for memory-to-memory data
movement.
The DMA controller controls data movement
over the entire XDATA memory space. Since
all the SFR registers (except some internal
registers) are mapped into the DMA memory
space these flexible DMA channels can be
used to unburden the 8051 in innovative ways,
e.g. feed a USART and I2S with data from
memory, periodically transfer samples
between ADC and memory, transfer data to
and from USB FIFOs (CC2511Fx) etc. Use of the
DMA can also reduce system power
consumption by letting the CPU run on a lower
frequency (CLKCON.CLKSPD) .
The main features of the DMA controller are as
follows:
• Five independent DMA channels
• Three configurable levels of DMA
channel priority
• 30 configurable transfer trigger events
• Independent control of source and
destination address
• Single, block and repeated transfer
modes
• Supports variable transfer length by
including the length field in the transfer
data
• Can operate in either word-size or
byte-size mode
13.2.1 DMA Operation
There are five DMA channels available in the
DMA controller numbered channel 0 to
channel 4. Each DMA channel can move data
from one place within the DMA memory space
to another.
In order to use a DMA channel it must first be
configured as described in sections 13.2.2 and
13.2.3.
Once a DMA channel has been configured it
must be armed before any transfers are
allowed to be initiated. A DMA channel is
armed by setting the appropriate bit in the
DMA Channel Arm register DMAARM.
When a DMA channel is armed a transfer will
begin when the configured DMA trigger event
occurs. There are 30 possible DMA trigger
events, e.g. UART transfer, Timer overflow
etc. The trigger event to be used by a DMA
channel is set by the DMA channel
configuration. The DMA trigger events are
listed in Table 42.
In addition to starting a DMA transfer through
the DMA trigger events, the user software may
force a DMA transfer to begin by setting the
corresponding DMAREQ bit.
Figure 12 shows the DMA state diagram.
CC2510Fx/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A Page 84 of 252