CC2510FX Datasheet, PDF (66/253 Pages) List of Unclassifed Manufacturers – True System-on-Chip with Low Power RF Transceiver and 8051 MCU

CC2510Fx / CC2511Fx
13 Peripherals
In the following sub-sections, each
CC2510Fx/CC2511Fx peripheral is described in
detail.
The CC2510Fx/CC2511Fx has four timers. These
timers all run on the tick frequency given by
the Power Management Controller register
CLKCON.TICKSPD.
13.1 I/O ports
Note: Note: P0_6 and P0_7 does not exist on
CC2511Fx. The CC2511Fx has 19 digital
input/output pins available and the ADC inputs
6 and 7 cannot be used. Apart from this, all
information in this section applies to both
CC2511Fx and CC2510Fx.
The CC2510Fx has 21 digital input/output pins
that can be configured as general purpose
digital I/O or as peripheral I/O signals
connected to the ADC, Timers, I2S or USART
peripherals. The usage of the I/O ports is fully
configurable from user software through a set
of configuration registers.
The I/O ports have the following key features:
• 21 digital input/output pins
• General purpose I/O or peripheral I/O
• Pull-up or pull-down capability on
inputs, except P1_0 and P1_1.
• External interrupt capability
The external interrupt capability is available on
all 21 I/O pins. Thus, external devices may
generate interrupts if required. The external
interrupt feature can also be used to wake up
from sleep modes.
13.1.1 General Purpose I/O
When used as general purpose I/O, the pins
are organized as three 8-bit ports, ports 0-2,
denoted P0, P1 and P2. P0 and P1 are
complete 8-bit wide ports while P2 has only
five usable bits (P2_0 to P2_4). All ports are
both bit- and byte addressable through the
SFR registers P0, P1 and P2. Each port pin
can individually be set to operate as a general
purpose I/O or as a peripheral I/O.
The output drive strength is 4 mA on all
outputs, except for the two high-drive outputs,
P1_0 and P1_1, which each have 20 mA
output drive strength.
To use a port as a general purpose I/O pin the
pin must first be configured. The registers
PxSEL where x is the port number 0-2 are
used to configure each pin in a port either as a
general purpose I/O pin or as a peripheral I/O
signal. By default, after a reset, all digital
input/output pins are configured as general-
purpose I/O pins.
By default, all general-purpose I/O pins are
configured as inputs. To change the direction
of a port pin, at any time, the registers PxDIR
are used to set each port pin to be either an
input or an output. Thus by setting the
appropriate bit within PxDIR to 1, the
corresponding pin becomes an output.
When reading the port registers P0, P1 and
P2, the logic values on the input pins are
returned regardless of the pin configuration.
This does not apply during the execution of
read-modify-write instructions. The read-
modify-write instructions when operating on a
port registers are the following: ANL, ORL,
XRL, JBC, CPL, INC, DEC, DJNZ and MOV,
CLR or SETB, when the destination is an
individual bit in a port register P0, P1 or P2.
For these read-modify-write instructions, the
value of the register, not the value on the pin,
is read, modified, and written back to the port
register.
When used as an input, the general purpose
I/O port pins can be configured to have a pull-
up, pull-down or tri-state mode of operation. By
default, after a reset, inputs are configured as
inputs with pull-up. To deselect the pull-
up/pull-down function on an input the
appropriate bit within the PxINP must be set to
1. The I/O port pins P1_0 and P1_1 do not
have pull-up/pull-down capability.
In power modes PM1, PM2 and PM3 the I/O
pins retain the I/O mode and output value (if
applicable) that was set when PM1/2/3 was
entered.
13.1.2 General Purpose I/O Interrupts
General purpose I/O pins configured as inputs
can be used to generate interrupts. The
interrupts can be configured to trigger on either
a rising or falling edge of the external signal.
Each of the P0, P1 and P2 ports have
separate interrupt enable bits common for all
bits within the port located in the IEN1-2
registers as follows:
CC2510Fx/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A Page 66 of 252