CC2510FX Datasheet, PDF (28/253 Pages) List of Unclassifed Manufacturers – True System-on-Chip with Low Power RF Transceiver and 8051 MCU

CC2510Fx / CC2511Fx
A block diagram of CC2510Fx/CC2511Fx is shown
in Figure 6. The modules can be roughly
divided into one out of three categories: CPU-
related modules, radio-related modules and
modules related to power, test and clock
distribution. In the following subsections, a
short description of each module that appears
in Figure 6 is given.
9.1 CPU and Peripherals
The 8051 CPU core is a single-cycle 8051-
compatible core. It has three different memory
access buses (SFR, DATA and
CODE/XDATA), a debug interface and an 18-
input extended interrupt unit. See section 12
for details.
The memory crossbar/arbitrator is at the
heart of the system as it connects the CPU
and DMA controller with the physical
memories and all peripherals through the SFR
bus. The memory arbitrator has four memory
access points, which can access three
physical memories: a 1/2/4 KB SRAM, 8/16/32
KB flash memory or SFR registers. The
memory arbitrator is responsible for performing
arbitration and sequencing between
simultaneous memory accesses to the same
physical memory.
The SFR bus is drawn conceptually in the
block diagram as a common bus that connects
all hardware peripherals to the memory
arbitrator. The SFR bus also provides access
to the radio registers in the radio register bank
even though these are indeed mapped into
XDATA memory space.
The 1/2/4 KB SRAM maps to the DATA
memory space and part of the XDATA/CODE
memory spaces. The memory is an ultra-low-
power SRAM that retains its contents even
when the digital part is powered off (power
modes 2 and 3).
The 8/16/32 KB flash block provides in-circuit
programmable non-volatile program memory
for the device and maps into the CODE and
XDATA memory spaces. Writing to the flash
block is performed through a flash controller
that allows page-wise (1024 byte) erasure and
byte-wise reprogramming. See section 13.16
for details.
A versatile five-channel DMA controller is
available in the system. It accesses memory
using a unified memory space (XDATA) and
has therefore access to all physical memories.
Each channel is configured (trigger event,
priority, transfer mode, addressing mode,
source and destination pointers, and transfer
count) with DMA descriptors anywhere in
memory. Many of the hardware peripherals
rely on the DMA controller for efficient
operation (AES core, flash controller, USARTs,
Timers and ADC interface) by performing data
transfers between a single SFR address and
flash/SRAM. See section 13.2 for details.
The interrupt controller services 18 interrupt
sources, divided into six interrupt groups, each
of which is associated with one out of four
interrupt priorities. An interrupt request is
serviced even if the device is in a sleep mode
(power modes 1-3) by bringing the
CC2510Fx/CC2511Fx back to active mode (power
mode 0).
The debug interface implements a proprietary
two-wire serial interface that is used for in-
circuit debugging. Through this debug
interface it is possible to perform an erasure of
the entire flash memory, control which
oscillators are enabled, stop and start
execution of the user program, execute
supplied instructions on the 8051 core, set
code breakpoints, and single step through
instructions in the code. Using these
techniques, it is possible to elegantly perform
in-circuit debugging and external flash
programming. See section 12.9 for details.
The I/O-controller is responsible for all
general-purpose I/O pins. The CPU can
configure whether peripheral modules control
certain pins or whether they are under
software control. If uses as I/O whether each
pin is configured as an input or output, and if a
pull-up or pull-down resistor in the pad is
connected. Each peripheral that connects to
the I/O-pins can choose between two different
locations to ensure flexibility in various
applications. See section 13.1 for details.
The sleep timer is an ultra-low power timer
that counts 32.768 kHz crystal oscillator or 32 -
34.6667 kHz RC oscillator periods. The sleep
timer runs continuously in all operating modes
except power mode 3. It can be configured in
one of several resolution modes, to strike the
right balance between timer resolution and
timeout period. Typical uses for it is as a real-
time counter that runs regardless of operating
mode (except power mode 3) or as a wakeup
timer to get out of power modes 1 or 2. See
section 13.5 for details.
A built-in watchdog timer allows the
CC2510Fx/CC2511Fx to reset itself in case the
CC2510Fx/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A Page 28 of 252