CC2510FX Datasheet, PDF (160/253 Pages) List of Unclassifed Manufacturers – True System-on-Chip with Low Power RF Transceiver and 8051 MCU

CC2510Fx / CC2511Fx
In full duplex both the RX and TX lines will
be used. Both the I2SCFG0.TXIEN and
I2SCFG0.RXIEN interrupt enable bits
must be set if interrupts are used and both
the DMA triggers I2STX and I2SRX may
be used.
When half duplex is used only one of the
RX and TX lines are typically connected.
Only the appropriate interrupt flag should
be set and only one of the DMA triggers
should be used.
13.14.8 Master Mode
The I2S is configured as a master device
by setting I2SCFG0.MASTER to 1. In
master mode the SCK and WS signals
are generated by the I2S.
13.14.8.1 Clock Generation
When the I2S is configured as master, the
frequency of the SCK clock signal must be
set to match the sample rate. The clock
frequency must be set before master
mode is enabled.
SCK is generated by dividing the system
clock using a fractional clock divider. The
amount of division is given by the 15 bit
numerator, NUM and 9-bit denominator,
DENOM as shown in the following
formula:
F_sck =
F_clk
NUM
2(
)
DENOM
where ^NUM > 3.35
DENOM
Where F_clk is the system clock frequency
and F_sck is the I2S SCK sample clock
frequency.
The numerator and denominator are set
by writing to the clock configuration
registers I2SCLKF0, I2SCLKF1 and
I2SCLKF2.
Please note that to stay within the timing
requirements of the I2S specification [3], a
minimum value of 3.35 should be used for
the (NUM / DENOM) fraction.
The fractional divider is made such that
most normal sample rates should be
supported for most normal word sizes with
a 24 MHz system clock frequency
(CC2511Fx). Examples of supported
configurations for a 24 MHz CLK is given
in Table 47. Table 48 shows the
configuration values for a 26 MHz system
clock frequency. Notice that the generated
I2S frequency is not exact for the 44.1
kHz, 16 bits word size configuration at 26
MHz. The numbers are calculated using
the following formulas, where F_s is the
sample rate and W is the word size:
F_s
=
F_sck
2 *W
CLKDIV = ^NUM = ^Fclk
DENOM 4 *W * F_s
F_sck (kHz)
8
8
44.1
48
Word Size (W)
8
16
16
16
CLKDIV
93.75
46.875
8.503401
7.8125
I2SCLKF2 I2SCLKF1
0x01
0x77
0x01
0x77
0x04
0xE2
0x00
0x7D
I2SCLKF0
0x04
0x08
0x93
0x10
Exact
yes
yes
yes
yes
Table 47 Example I2S Clock Configurations (CC2511Fx, 24 MHz)
F_sck (kHz) Word Size (W)
8
8
8
16
CLKDIV
101.5625
50.78125
I2SCLKF2 I2SCLKF1
0x06
0x59
0x06
0x59
I2SCLKF0
0x10
0x20
Exact
yes
yes
CC2510Fx/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A Page 160 of
252