CC2510FX Datasheet, PDF (89/253 Pages) List of Unclassifed Manufacturers – True System-on-Chip with Low Power RF Transceiver and 8051 MCU

CC2510Fx / CC2511Fx
13.2.5 DMA Interrupts
Each DMA channel can be configured to
generate an interrupt to the CPU upon
completing a DMA transfer. This is
accomplished with the IRQMASK bit in the
channel configuration. The corresponding
interrupt flag in the DMAIRQ SFR register will
be set when the interrupt is generated.
Regardless of the IRQMASK bit in the channel
configuration, the interrupt flag will be set upon
DMA channel complete. Thus software should
always check (and clear) this register when
rearming a channel with a changed IRQMASK
setting. Failure to do so could generate an
interrupt based on the stored interrupt flag.
13.2.6 DMA Configuration Data Structure
For each DMA channel, the DMA configuration
data structure consists of eight bytes. The
configuration data structure is described in
Table 43.
13.2.7 DMA USB Endianess (CC2511Fx)
When a USB FIFO is accessed using word
transfer DMA the endianess of the word
read/written can be controlled by setting the
ENDIAN.USBWLE and ENDIAN.USBRLE
configuration bits in the ENDIAN register. See
section 13.15 for details.
CC2510Fx/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A Page 89 of 252