CC2510FX Datasheet, PDF (223/253 Pages) List of Unclassifed Manufacturers – True System-on-Chip with Low Power RF Transceiver and 8051 MCU

CC2510Fx / CC2511Fx
0xDF04: PKTCTRL0 – Packet automation control
Bit Field Name
Reset R/W Description
7-
0
6 WHITE_DATA
1
5:4 PKT_FORMAT[1:0]
00
3 CC2400_EN
0
2 CRC_EN
1
1:0 LENGTH_CONFIG[1:0]
01
R0 Reserved
R/W Turn data whitening on / off
0: Whitening off
1: Whitening on
Data whitening can only be used when
PKTCTRL0.CC2400_EN = 0 (default).
R/W Format of RX and TX data
Setting Packet format
0 (00) Normal mode, use FIFOs for RX and TX
1 (01)
Serial Synchronous mode, used for backwards
compatibility
2 (10)
Random TX mode; sends random data using PN9
generator. Used for test.
Works as normal mode, setting 0 (00), in RX.
3 (11) ^{Asynchronous transparent mode. Data in on GDO0}
and Data out on either of the GDO pins
R/W Enable CC2400 support. Use same CRC implementation as
CC2400.
PKTCTRL0.WHITE_DATA must be 0 if
PKTCTRL0.CC2400_EN = 1.
R/W 1: CRC calculation in TX and CRC check in RX enabled
0: CRC disabled for TX and RX
R/W Configure the packet length
Setting Packet length configuration
0 (00) Fixed length packets, length configured in
PKTLEN register
1 (01) Variable length packets, packet length configured
by the first byte after sync word
2 (10) Enable infinite length packets
3 (11) Reserved
Bit Field Name
7:0 DEVICE_ADDR[7:0]
0xDF05: ADDR – Device address
Reset R/W Description
0x00
R/W Address used for packet filtration. Optional broadcast
addresses are 0 (0x00) and 255 (0xFF).
Bit Field Name
7:0 CHAN[7:0]
0xDF06: CHANNR – Channel number
Reset
R/W Description
0x00
R/W The 8-bit unsigned channel number, which is multiplied by
the channel spacing setting and added to the base
frequency.
CC2510Fx/CC2511Fx PRELIMINARY Data Sheet (Rev. 1.2) SWRS055A Page 223 of
252