GM82C803CN Datasheet, PDF (7/84 Pages) List of Unclassifed Manufacturers – 2.88 MB FDC/ Dual UARTs with FIFO/PIO(EPP/ ECP)/ IDE Interface/ S-IR/ PnP

GM82C803CN
(Continued)
PIN NO.
59
PIN
NAME
SLCT
BUFFER
TYPE
In
DESCRIPTION
Printer Selected Status pin. This high active output from the
printer indicates that it has power on. Bit 4 of the Printer Status
Register reads the SLCT input. Refer to Parallel Port description
for use of this pin in ECP and EPP mode.
75
ERROR
In
A low on this input from the printer indicates that there is an error
condition at the printer. Bit 3 of the Printer Status register reads
the ERR input . Refer to Parallel Port description for use of this
pin in ECP and EPP mode.
63-66 _{PD7-PD0 In/Out}
68-71
Port Data pin. The bi-directional parallel data bus is used to
transfer information between the chip and peripherals.
100 IOCH-
Out
In EPP mode, this pin is pulled low to extend the read/write
RDY
command. This pin has an internal pull-up.
5) IDE/16 BIT ADDRESS QUALIFICATION/ ALT IR PINS
24
IDEEN
In
IDE Enable pin. This active low signal is active when the IDE is
(Note) enabled and the I/O address is accessing an IDE register.
IRQ_H
The interrupt request from a logical device or IRQIN may be
Out
output on the IRQ_H signal. Refer to the configuration registers
for more information.
If EPP or ECP Mode is enabled, this output is pulsed low, then
released to allow sharing of interrupts.
25
HDCS0
Out
IDE Chip Select pin. This is the Hard Disk Chip select
(Note) ^{corresponding to the eight control block addresses.}
IRRX2
In
IR Receive pin. Alternate IR Receive input.
26 HDCS1
Out
IDE Chip Select pin. This is the Hard Disk Chip select
(Note) ^{corresponding to the alternate status register.}
IRTX2
IR Transmit pin. Alternate IR Transmit output.
6) MISCELLANEOUS
20 CLK14 ICLK
23 IRQIN
In
58 PWRGD
In
GAMECS Out
Clock pin. The external connection to a single source 14.318
MHz clock.
This pin is used to steer an interrupt signal from an external device
onto one of eight IRQ outputs, IRQA-H.
This active high input indicates that the power (Vcc) is valid. For
device operation, PWRGD must be active. When PWRGD is
inactive, all outputs are put into high impedance. The contents of
all registers are preserved as long as Vcc has a valid value. The
driver current drain in this mode drops to ISTBY (standby
current). This input has an internal pull-up.
This is the Game Port Chip Select output active low. It will go
active when the I/O address, qualified by AEN, matches that
selected in Configuration Register GDR.