GM82C803CN Datasheet, PDF (25/84 Pages) List of Unclassifed Manufacturers – 2.88 MB FDC/ Dual UARTs with FIFO/PIO(EPP/ ECP)/ IDE Interface/ S-IR/ PnP

GM82C803CN
The readIntr Threshold can be determined by setting the direction bit to 1 and filling the empty tFIFO with a byte at a
time until serviceIntr is set. This may generate a spurious interrupt, but will indicate that the threshold has been reached.
Data bytes are always read from the head of tFIFO regardless of the values of the direction bit. For example, if 44h, 33h,
22h are written to the FIFO, then reading the tFIFO will return 44h, 33h, 22h in the same order as they were written.
cnfgA (0x400 mode 111)
This configuration register is read only register. When read, 10h is returned. This indicates to the system that this is
an 8-bit implementation.
cnfgB (0x401 mode 111)
This configuration register is read only register.
Bit 77 Bi6t 6 B5it 5 4Bit 4 3Bit 3 2Bit 21 Bit01 Bit 0
0
0 0 0000
ecr (0x402 mode all)
This bit returns the values on the ISA IRQ line to determine the possible conflicts.
Bit 77 B6it 6 B5it 5 ^4Bit 4 ^3Bit 3 ² Bit ¹² Bit01 Bit 0
Empty : Read only
1: The FIFO is completely empty
0: The FIFO contains at least 1 byte of data.
Full : Read only
1: The FIFO cannot accept another byte or the FIFO is
completely full
0: The FIFO has at least 1 free byte.
Service Intr : Read/Write
1: Disables DMA and all of the service interrupts
0: Enables one of the following 3 cases of interrupts. Once one of the 3
service interrupts has occurred, serviceIntr bit shall be set to 1 by hard-
ware, and it must be reset to 0 to re-enable the interrupts.
case dmaEn =1:
During DMA (this bit is set to 1 when terminal count is reached).
case dmaEn =0 direction = 0:
This bit shall be set to 1 whenever there are writeIntrThreshold or more
free in FIFO
case dmaEn =0 direction =1:
This bit shall be set to 1 whenever there are readIntrThreshold or more
valid bytes to the read from the FIFO.
DMA En : Read/Write
1: Enables DMA (DMA starts when serviceIntr is 0).
0: Disables DMA unconditionally.
Err Intr En : Read/Write (Valid only in ECP mode)
1: Disables the interrupt generated on the asserting edge of nFault
0: Enables an interrupt pulse on the high to low edge of Fault. Note that an interrupt will
be generated if Fault is asserted (interrupting) and this bit is written from 1 to 0.
This prevents interrupt from being lost in the time between the read of the ECR and the
write of the ECR.
These bits are Read/Write and select the Mode. See the table 4-5.