GM82C803CN Datasheet, PDF (36/84 Pages) List of Unclassifed Manufacturers – 2.88 MB FDC/ Dual UARTs with FIFO/PIO(EPP/ ECP)/ IDE Interface/ S-IR/ PnP

GM82C803CN
If the FDC is in the DMA mode, no interrupts are generated during the execution phase. The FDC generates DRQ’s
(DMA Requests) when each byte of data is available. The DMA controller responds to this request with both a
DACK=0 (DMA Acknowledge) and a RD=0 (host read). If a Write Command has been programmed then a host
write signal will appear instead of host read. After the execution phase has been completed (TC occurred), then an
interrupt will occur (IRQ6=1). This signifies the beginning of the result phase. When the first byte of data is read
during the result phase, the interrupt is automatically reset (IRQ=0).
Command Parameters
The FDC is capable of executing 23 different commands. Each command is initiated by a multibyte transfer from the processor,
and the result after execution of the command may also be a multi-byte transfer back to the processor. Because of this multi-byte
interchange of information between the FDC and the processor, it is convenient to consider each command as consisting of thr-
ee phases;
- Command Phase : The FDC receives all information required to perform a particular operation from the processor.
- Execution Phase : The FDC performs the operation it was instructed to do.
- Result Phase : After completion of the operation, status and other housekeeping information are made available to the
processor.
Table 4 - 19 Command List
Read Data
Read Deleted Data
Write Data
Write Deleted Data
Read a Track
Read ID
Formal a Track
Scan Equal
Scan Low or Equal
Scan High or Equal
Recalibrate
Sense Interrupt Status
Specify
Sense Drivers Status
Seek
Verify
Version
Lock
Configure
Relative Seek
Dumpreg
Perpendicular Mode
Invalid