GM82C803CN Datasheet, PDF (29/84 Pages) List of Unclassifed Manufacturers – 2.88 MB FDC/ Dual UARTs with FIFO/PIO(EPP/ ECP)/ IDE Interface/ S-IR/ PnP

GM82C803CN
Transfer from the HOST to the FIFO
In the forward direction, an interrupt occurs when service interrupt is 0 and there are writeIntrThreshold or more bytes
free in the FIFO. At this time if the FIFO is empty, it can be filled with a single burst before the empty bit needs to be
re-read. Otherwise it may be filled with WriteIntrThreshold byte. If an interrupt occurs, the host must respond to
therequest by writing data to the FIFO.
Transfer from the FIFO to the HOST
In the backward direction, an interrupt occurs when service interrupt is 0 and there are readIntrThreshold or more
bytes are available in the FIFO. At this time if the FIFO is full, it can be emptied completely in a single burst.
Otherwise it may be filled with WriteIntrThreshold bytes. If an interrupt occurs, the host must respond to the request
by reading data from the FIFO.
ECP FORWARD (WRITE) OPERATION
1. An ECP write cycle starts when the ECP drives the popped tag onto AFD and the popped byte onto PD<7:0>.
2. When BUSY is low, the ECP asserts STROBE and waits for BUSY to be high.
3. When BUSY is high, the ECP deasserts STROBE.
4. The ECP may change AFD and PD<7:0> in preparation for next cycle when BUSY is low.
ECP BACKWARD (READ) OPERATION
1. An ECP read cycle starts when the ECP drives AFD low.
2. The peripheral device drives BUSY high for a normal data read cycle, or drives BUSY low for a command
read cycle and drives the byte to be read onto PD<7:0>.
3. When ACK is asserted, the ECP reads the PD<7:0> and drives AFD high.
4. When AFD is high, the peripheral device deasserts ACK and may change BUSY and PD<7:0> in preparation
for the next cycle.