GM82C803CN Datasheet, PDF (11/84 Pages) List of Unclassifed Manufacturers – 2.88 MB FDC/ Dual UARTs with FIFO/PIO(EPP/ ECP)/ IDE Interface/ S-IR/ PnP

GM82C803CN
3.1.7 Parallel Port base Address Register (PAR)
Index = C6
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ADR2
ADR3
ADR4
ADR5
ADR6
ADR7
ADR8
ADR9
This register is used to select the base address of the parallel port.
If EPP is not enabled, the parallel port can be set to 192 locations, on 4 byte boundaries form 100h-3FCh.
If EPP is enabled, the parallel port can be set to 96 locations, on 8 byte boundaries from 100h-3F8h.
Upper address decode requirements : CS = ??and A10 =??are required to access the parallel port
when not ECP mode. (A10 active : when in ECP mode)
3.1.8 First Serial port base address Register (FSR)
Index = C7
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0
ADR3
ADR4
ADR5
ADR6
ADR7
ADR8
ADR9
This register is used to select the base address of the UART1.
The serial port can be set to 96 locations on 8 byte boundaries from 100H-3F8H.
Upper address decode requirements : CS = ??and A10 =??are required to access UART 1 registers.
A[3:0] are decoded as 0xxxb
3.1.9 Second Serial port base address Register (FSR)
Index = C8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0
ADR3
ADR4
ADR5
ADR6
ADR7
ADR8
ADR9
This register is used to select the base address of the UART2.
The serial port can be set to 96 locations on 8 byte boundaries from 100H-3F8H.
Upper address decode requirements : CS = ??and A10 =??are required to access UART 2 registers.
A[3:0] are decoded as 0xxxb