GM82C803CN Datasheet, PDF (60/84 Pages) List of Unclassifed Manufacturers – 2.88 MB FDC/ Dual UARTs with FIFO/PIO(EPP/ ECP)/ IDE Interface/ S-IR/ PnP

GM82C803CN
Bit 4 : This bit is the Even Parity Select bit. When bit 3 is logic 1 and bit 4 is logic 0, odd number of logic 1s is
transmitted or checked in the data word bits and parity bit. When bit 3 is logic 1 and bit 4 is a logic 1, an even
number of logic 1s is transmitted or checked.
Bit 5 : This bit is the Stick Parity bit. When bit 3,4 and 5 are logic 1, the parity bit is transmitted and checked as
logic 0. If bit 3 and 5 are 1 and bit 4 is logic 0, then the parity bit is transmitted and checked as logic 1. If bit 5 is
logic 0, Stick parity is disabled.
Bit 6 : This bit is the Break Control bit. When it is set to logic 1, the serial output (SOUT) is forced to the Spacing
(logic 0) state. The break is disabled by setting bit 6 to logic 0. The Break Control bit acts only on SOUT and has no
effect on the transmitter logic.
* Note : This feature enables the CPU to alert a terminal. During the break, the transmitter can be used as a
character time to accurately establish the break duration in a computer communication system.
Bit 7 : This bit is the Divisor Latch Access Bit (DLAB). It must be set high (logic 1) to access the Divisor Latches
of the Baud Rate Generator during a read or write operation. It must be set low (logic 0) to access the Receiver
Buffer, the Transmitter Holding Register, or the Interrupt Enable Register.
Line Status Register
This register provides status information to the CPU concerning the data transfer. Table 4-30. shows the contents of
the Line Status Register. Details on each bit follow :
Bit 0 : This bit is the receiver Data Ready (DR) indicator. Bit 0 is set to logic 1 whenever a complete incoming
character has been received and transferred into the Receiver Buffer Register or the FIFO. Bit 0 is reset to logic 0 by
reading all of the data in the Receiver Buffer Register or the FIFO.
Bit 1 : This bit is the Overrun Error (OE) indicator. Bit 1 indicates that data in the Receiver Buffer Register was not
read by the CPU before the next character was transferred into the Receiver Buffer Register, thereby destroying the
which causes elimination of the previous character. The OE indicator is set to logic 1 upon detection of an overrun
condition and reset whenever the CPU reads the contents of the Line Status Register. If the FIFO mode data
continues to fill the FIFO beyond the trigger level, an overrun error will occur only after the FIFO is full and the next
character has been completely received in the shift register. The OE is indicated to the CPU as soon as it happens.
The character in the shift register is overwritten, but it is not transferred to the FIFO.
Bit 2 : This bit is the Parity Error (PE) indicator. Bit 2 indicates that the received data character does not have the
correct even or odd parity, as selected by the even-parity-select bit. The PE bit is set to a logic 1 upon detection of a
parity error and is reset to logic 0 whenever the CPU reads the contents of the Line Status Register. In the FIFO
mode, this error is associated with the particular character in the FIFO it applies to. This error is detected by CPU
when its associated character is at the top of the FIFO.
Bit 3 : This bit is the Framing Error (FE) indicator. Bit 3 indicates that the received character does not have a valid
stop bit. Bit 3 is set to logic 1 whenever the stop bit following the last data bit or parity bit is detected as logic 0
(Spacing level). The FE indicator is reset whenever the CPU reads the contents of the Line Status Register. In the
FIFO mode, this error is associated with the particular character in the FIFO it applies to. This error is detected by the
CPU when its associated character is at the top of the FIFO. The UART will try to resynchronize after a framing
error. To do this, it assumes that the framing error was due to the next start bit so it samples this tart?bit twice and
then takes in the ata?
Bit 4 : This bit is the Break Interrupt (BI) indicator. Bit 4 is set to a logic 1 whenever the received data input is held
in the Spacing (logic 0) state for longer than a full word transmission time. (that is, the total time of start bit + data
bits + parity + stop bit). The BI indicator is reset whenever the CPU reads the contents of the Line Status Register. In
the FIFO mode, this error is associated with the particular character in the FIFO it applies to.