GM82C803CN Datasheet, PDF (24/84 Pages) List of Unclassifed Manufacturers – 2.88 MB FDC/ Dual UARTs with FIFO/PIO(EPP/ ECP)/ IDE Interface/ S-IR/ PnP

GM82C803CN
dcr (0x002 : Device Control Register)
This register directly controls several output signals as well as enabling some functions. The drivers for Strobe,
AutoFd, Init, and SelectIn are open-collector in mode 000, and are push-pull in all other modes.
Table. Device Control Register
<7:6>
R
<5>
R/W
1:
0:
<4>
R/W
1:
0:
<3>
R/W
<2>
R/W
<1>
R/W
<0>
R/W
Reserved, returns undefined when read.
Direction
If mode = 000 or mode = 010, we are standard parallel port and this bit has
no effect (drivers are enabled). Otherwise, this bit tri-states the drivers and
sets the direction so that data will be read from the peripheral.
Drivers are enabled. DMA, data are written to the peripheral.
ackIntEn
Enables an interrupt on the rising edge of Ack.
Disables the Ack interrupt.
SelectIn is inverted and then driven as parallel port SelectIn.
Init is driven as parallel port Init.
AutoFd is inverted and then driven as parallel port AutoFd.
Strobe is inverted and then driven as parallel port Strobe.
cFifo (0x400 , Mode = 010 : Parallel Port Data FIFO)
Data written or DMAed from the system to this FIFO are transmitted by a hardware handshake to the peripheral
using the standard parallel port protocol. Transfers to the FIFO are PWord aligned. If odd bytes need to be
transferred then the operation must be handled in mode 000. This mode is only defined for the forward direction.
ecpDFifo (0x400 , Mode = 011 : ECP Data FIFO)
Data written or DMAed from the system to these FIFO when direction is 0 are transmitted to the peripheral by
hardware handshake using the ECP parallel port protocol, Transfers to the FIFO are PWord-aligned. Ifodd bytes
need to be transferred then the operation must be handled in mode 000.
Data from the peripheral are read under automatic hardware handshake from ECP into this FIFO when direction is
1. Reads or DMAs from the FIFO will return ECP data to the system.
tFifo (0x400 mode 110)
Data bytes may be read, written or DMAed to or from the system to this FIFO in any direction.
Data in the tFIFO will not be transmitted to the parallel port lines using a hardware protocol handshake. However,
data in the tFIFO may be displayed on the parallel port lines.
The tFIFO will not stall when overwritten or underrun. If an attempt is made to write data into a full tFIFO, the new
data is not accept into the tFIFO. If an attempt is made to read data from an empty tFIFO, the last data byte is re-read.
The full and empty bits must always keep track of the correct FIFO state. The tFIFO will transfer data at the maximum
ISA rate so that software may generate performance merits.
The FIFO size and the interrupt threshold can be determined by writing bytes to the FIFO and checking the full and
serviceIntr bits.
The writeIntrThreshold can be determined by starting with a full tFIFO, setting the direction bit to 0 and emptying it
a byte at a time until serviceIntr is set. This may generate a spurious interrupt, but will indicate that the threshold has
been reached.