GM82C803CN Datasheet, PDF (61/84 Pages) List of Unclassifed Manufacturers – 2.88 MB FDC/ Dual UARTs with FIFO/PIO(EPP/ ECP)/ IDE Interface/ S-IR/ PnP

GM82C803CN
This error is detected by the CPU when its associated character is at the top of the FIFO. When break occurs only one
zero character is loaded into the FIFO. The next character transfer is enabled after SIN goes to the marking state and
receives the next valid start bit.
Note : Bits 1 through 4 are the error conditions that produce a Receiver Line Status interrupt whenever any of the
corresponding conditions are detected and the interrupt is enabled.
Bit 5 : This bit is the Transmitter Holding Register Empty (THRE) indicator. Bit 5 indicates that the UART is ready
to accept a new character for transmission. In addition, this bit causes the UART to issue an interrupt to the CPU
when the Transmitter Holding Register Empty Interrupt enable is set high. The THRE bit is set to logic 1 when a
character is transferred from the Transmitter Holding Register into the Transmitter Shift Register. The bit is reset to
logic 0 concurrently with the loading of the Transmitter Holding Register by the CPU.In the FIFO mode, this bit is set
when the XMIT FIFO is empty ; it is cleared when at least 1 byte is written to the XMIT FIFO.
Bit 6 : This bit is the Transmitter Empty (TEMT) indicator. Bit 6 is set to a logic 1 whenever the Transmitter Holding
Register (THR) and the Transmitter Shift Register (TSR) are both empty. It is reset to logic 0 whenever either the
THR or TSR has a data character. In the FIFO mode, this bit is set to one whenever both the transmitter FIFO and
shift register are empty.
Bit 7 : In the GM16C450 Mode, this is logic 0. In the FIFO mode, LSR 7 is set when there is at least one parity error,
framing error or break indication in the FIFO. LSR 7 is cleared when the CPU reads the LSR, if there are no
subsequent errors in the FIFO.
* Note : The Line Status Register is only for read operations. Writing to this register is not recommended as this
operation is only used for factory testing.
FIFO Control Register
This is a write only register at the same location as the IIR (the IIR is a read only register). This register is used to
enable the FIFOs, clear the FIFOs, set the RCVR FIFO trigger level, and select the type of DMA signaling.
Bit 0 : Writing a 1 to FCR 0 enables both the XMIT and RCVR FIFOs. Resetting FCR 0 will clear all bytes in both
FIFOs. When changing from FIFO Mode to GM16C450 Mode and vice versa, data is automatically cleared from the
FIFOs. This bit must be a 1 when other FCR bits are written to or they will not be programmed.
Bit 1 : Writing a 1 to FCR 1 clears all bytes in the RCVR FIFO and resets its counter logic to 0. The shift register is
not cleared. The 1 written to this bit position is self-clearing.
Bit 2 : Writing a 1 to FCR 2 clears all bytes in the XMIT FIFO and resets its counter logic to 0. This shift register is
not cleared. The 1 written to this bit position is self-clearing.
Bit 3 : Setting FCR 3 to a 1 will cause the RXRDY and TXRDY pins to change from mode 0 to mode 1 if FCR 0 = 1
Bit 4,5 : FCR 4 and FCR 5 are reserved for future use.
Bit 6,7 : FCR 6 and FCR 7 are used to set the trigger level for the RCVR FIFO interrupt.
Table 4-31. RCVR FIFO
7
6
RCVR FIFO
Trigger Level (Bytes)
0
0
01
0
1
04
1
0
08
1
1
14