GM82C803CN Datasheet, PDF(13/84 Page) List of Unclassifed Manufacturers – 2.88 MB FDC/ Dual UARTs with FIFO/PIO(EPP/ ECP)/ IDE Interface/ S-IR/ PnP

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GM82C803CN Datasheet, PDF (13/84 Pages) List of Unclassifed Manufacturers – 2.88 MB FDC/ Dual UARTs with FIFO/PIO(EPP/ ECP)/ IDE Interface/ S-IR/ PnP

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GM82C803CN

3.1.13 In IRQ selection Register (IIR)

Index = CD

This register is used to select the IRQ for IRQIN (bits 3:0), bits 7:4 are reserved and return zero when read.

Any unselected IRQ output (registers : IIR, SIR, IRR) is in tristate.

3.1.14 UART Mode Register (UMR)

Index = CE

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

UART 2 RX input inverting enable.

UART 2 TX output inverting enable.

UART 2 half duplex enable.

UART 2 mode (SeeTable 3-2).

This register controls the operating mode of the UART.

UART 1 high speed enable.

UART 2 high speed enable.

Bit 5 Bit 4 Bit 3

UART 2 MODE

Standard (Default)

IrDA (HPSIR)

0 Amplitude Shift Keyed IR @ 500KHz

Reserved

(Table 3-2. UART 2 MODE)

3.1.15 Power Down Register (PDR)

Index = CF

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

All

FDC Power Down

UART 1 Power Down

UART 2 Power Down

Parallel port Power Down

Clock Power Down

Reserved

This register controls which part falls in power down mode.

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