GM82C803CN Datasheet, PDF (64/84 Pages) List of Unclassifed Manufacturers – 2.88 MB FDC/ Dual UARTs with FIFO/PIO(EPP/ ECP)/ IDE Interface/ S-IR/ PnP

GM82C803CN
Bit 0 : This bit is the Delta Clear to Send (DCTS) indicator. Bit 0 indicates that the CTS input to the chip has changed
state since the last time it was read by the CPU.
Bit 1 : This bit is the Delta Data Set Ready (DDSR) indicator. Bit 1 indicates that the DSR input to the chip has
changed state since the last time it was read by the CPU
Bit 2 : This bit is the Trailing Edge of Ring Indicator (TERI) detector. Bit 2 indicates that the RI input to the chip has
changed from a low to a high state.
Bit 3 : This bit is the Delta Data Carrier Detect (DDCD) indicator. Bit 3 indicates that the DCD input to the chip has
changed state.
* Note : Whenever bit 0, 1, 2 or 3 is set to logic 1, a Modem Status Interrupt is generated.
Bit 4 : This bit is the complement of the Clear to Send (CTS) input. If bit 4 (loop) of the MCR is set to 1, this bit is
equivalent to RTS in the MCR.
Bit 5 : This bit is the complement of the Data Set Ready (DSR) input. If bit 4 of the MCR is set to 1, this bit is
equivalent to DTR in the MCR.
Bit 6 : This bit is the complement of the Ring Indicator (RI) input. If bit 4 of the MCR is set to 1, this bit is equivalent
to OUT1 in the MCR.
Bit 7 : This bit is the complement of the Data Carrier Detect (DCD) input. If bit 4 of the MCR is set to 1, this bit is
equivalent to OUT2 in the MCR.
Scratch Register
This 8-bit Read/Write Register does not control the UART in any way. It is intended as a scratchpad register to be used
by the programmer to hold data temporarily.
FIFO Interrupt Mode Operation
When the RCVR FIFO and receiver interrupts are enabled (FCR 0 = 1, IER 0 = 1) RCVR interrupts occur as follows :
1) The received data available interrupt will be issued to the CPU when the FIFO has reached its programmed trigger
level; it will be cleared as soon as the FIFO drops below its programmed trigger level.
2) The IIR receive data available indication also occurs when the FIFO trigger level is reached, and like the interrupt,
it is cleared when the FIFO drops below the trigger level.
3) The receiver line status interrupt (IIR-06), as before, has higher priority than the received data available (IIR-04)
interrupt.
4) The data ready bit (LSR 0) is set as soon as a character is transferred from the shift register to the RCVR FIFO.
It is reset when the FIFO is empty.
When RCVR FIFO and receiver interrupts are enabled, RCVR FIFO timeout interrupts occurs as follows :
1) A FIFO timeout interrupt occurs if the following conditions exist :
- at least one character is in the FIFO
- the most recent serial character received was longer than 4 continuous character times ago (if 2 stop bits are
programmed, the second one is included in this time delay).
- the most recent CPU read of the FIFO was longer than 4 continuous character times ago.
This will cause a maximum character received to interrupt issued delay of 160 ms at 300 baud with a 12 bit character.
2) Character times are calculated by using the RCLK input for a clock signal (this makes the delay proportional to the
baud rate).