GM82C803CN Datasheet, PDF (62/84 Pages) List of Unclassifed Manufacturers – 2.88 MB FDC/ Dual UARTs with FIFO/PIO(EPP/ ECP)/ IDE Interface/ S-IR/ PnP

GM82C803CN
Interrupt Identification Register
In order to provide minimum software overhead during data character transfers, the UART identifies interrupts into
four levels and records these in the Interrupt Identification Register. The four levels of interrupt conditions are
1.Receiver Line Status ; 2.Received Data Ready ; 3.Transmitter Holding Register Empty ; and 4.in order of priority
Modem Status. When the CPU accesses the IIR, the UART freezes all interrupts and indicates the highest priority
pending interrupt to the CPU. While this CPU access is occurring, the UART records new interrupts, but does not
change its current indication until the access is complete. Details on each bit follow :
Bit 0 : This bit can be used in a prioritized interrupt environment to indicate whether an interrupt is pending. When bit
0 is logic 0, an interrupt is pending and the IIR contents may be used as a pointer to the appropriate interrupt service
routine. When bit 0 is logic 1, no interrupt is pending.
Bit 1 and 2 : These two bits are used to identify the highest priority interrupt pending.
Bit 3 : In the GM16C450 Mode, this bit is 0. In the FIFO mode, this bit is set along with bit 2 when a timeout interrupt
is pending.
Bit 4 and 5 : These two bits are always logic 0.
Bit 6 and 7 : These two bits are set when FCR 0 = 1
Table 4-32. Interrupt Identification Table
Bit 3 Bit 2
0
0
0
1
1
1
0
0
0
0
Bit 1 Bit 0
0
1
0
0
0
0
1
0
0
0
Priority
-
Second
Second
Third
Fourth
Type
No
interrupt
Source
Receiver
Line
Status Error
Reset
Control
Reading the
Line Status
Register
Received
Data
Available
Receiver
Data
Available
Read Receiver
Buffer or
the FIFO
drops below the
trigger level
Character
Timeout
Indication
During 4
character time
the number of
data in Receiver
FIFO is not
changed and
there is at least
1 character
in it
Reading the
Receiver
Buffer
Register
Transmitter
Holding
Register
Empty
Transmitter
Holding
Register
Empty
Reading the
IIR or Writing
the Transmitter
Holding
Register
Modem
Status
Modem
Input
Signal
Change
Reading the
Modem Status
Register