GM82C803CN Datasheet, PDF (53/84 Pages) List of Unclassifed Manufacturers – 2.88 MB FDC/ Dual UARTs with FIFO/PIO(EPP/ ECP)/ IDE Interface/ S-IR/ PnP

GM82C803CN
Seek
The read / write head within the FDD is moved from cylinder to cylinder under the control of the Seek command .
FDC has four independent Present Cylinder Registers each drive. they are cleared only after the Recalibrate command
. The FDC compares the PCN(Present Cylinder Number) which is the current head position with the NCN(New
Cylinder Number ) , and if there is a difference , performs the following operation :
PCN < NCN : Direction signal to FDD set to a 1 , and step pulses are issued (In)
PCN > NCN : Direction signal to FDD set to a 0 , and step pulses are issued (Out)
The rate art which step pulses are issued is controlled by SRT(Stepping Rate Time) in the Specify command . After
each step pulse is issues NCN is compares against PCN , and when NCN = PCN , the SE(Seek End) flag is set in
Status Register 0 to a 1 , and the command is terminated . At this point FDC interrupt goes high . Bits0-3 in the Main
Status Register are set during the Seek operation , and are cleared by the Sense Interrupt States command . During the
command phase of the Seek operation , the FDC is in the FDC busy state . But during the execution phase , it is the
non -busy state . While the FDC is in the non-busy state , another Seek command may be issued for as long as the
FDC is in the process of sending step pulses to any drive.
If the time to write three bytes of Seek command exceeds 150 , between the first two step pulses may be shorter
then set in the Specify command by as much as 1
Recalibrate
The function of this command is to retract the read /write head within the FDD to the Track 0 position. The FDC
clears the contents of the PCN counter and checks the status of the Track 0 signal from the FDD . As long as the
Track 0 signal is low , the directionsignal remains 0 and step pulses are issued . When the Track 0 signal goes 1, the
SE(Seek End) flag in States Register 0 is set to a 1 and the command is terminated. If the Track 0 signal is still 0 after
255 step pulses have been issued , the FDC sets the SE and EC(Equipment Check) flags of Status Register 0 to both
1s , and terminates the command after bits 7 and 6 of Status Register 0 are set to 0 and 1 respectively.
The ability to do overlap Recalibrate commands to multiple FDDs and load of the Ready signal , as described the Seek
command , also applies to Recalibrate command.
Sense Interrupt Status
An Interrupt signal is generated by the FDC for one of the following reasons :
1. Upon entering the result phase of :
a. Read Data command
b. Read a Track command
c. Read ID command
d. Read Deleted Data command
e. Write Data command
f. Format a Track command
g. Write Deleted Data command
h. Scan commands
i. Verify command
2. Read line of FDD changes state
3. End of Seek or Recalibrate command
4. During execution phase in the non-DMA mode
Interrupts caused by reasons 1 and 4 above occur during normal command operations and easily discernible by the
processor . During an execution phase in non-DMA,bit4 in the Main Status Register is 1. Upon entering the result
phase , this bit gets cleared . Reasons 1 and 4 do not require Sense Interrupt Status commands. The interrupt is
cleared by read /write data to the FDC . Interrupts caused by reason 2 and 3 above may be uniquely identified with the
aid of the Sense Interrupt Status command . this command , when issued results the Interrupt signal and via bits
5,6,and 7 of Status Register 0 identifies the cause of the interrupt.