GM82C803CN Datasheet, PDF (5/84 Pages) List of Unclassifed Manufacturers – 2.88 MB FDC/ Dual UARTs with FIFO/PIO(EPP/ ECP)/ IDE Interface/ S-IR/ PnP

GM82C803CN
(Continued)
PIN NO. PIN
NAME
88
89
78
79
81, 91
RXD2/
IRRX
TXD2/
IRTX
RXD1
TXD1
RTS1,
RTS2
83, 93 DTR1,
DTR2
82, 92
CTS1,
CTS2
80, 90
DSR1,
DSR2
85, 87 DCD1,
DCD2
BUFFER
TYPE
DESCRIPTION
3) SERIAL PORT INTERFACE
In
Receive Data pin. Receiver serial data input for port 2. IR
Receive Data.
Out
Transmit Data pin. Receiver serial data output for port 2. IR
Transmit Data.
In
Receive Data pin. Receiver serial data input for port 1.
Out
Transmit Data pin. Transmit serial data output for port 1.
Out
Active low Request To Send outputs for the serial port.
Handshake out put signal notifies modem that the UART is ready
to transmit data. This signal can be programmed by writing to
bit 1 of Modem Control Register (MCR). The hardware reset will
reset the RTS signal to inactive mode (high). Forced inactive
during loop mode operation.
Out
Active low Data Terminal Ready outputs for the serial port.
Handshake output signal notifies modem that the UART is ready
to establish data communication link. This signal can be
programmed by writing to bit 0 of Modem Control Register
(MCR). The hardware reset will reset the DTR signal to inactive
mode (high). Forced inactive during loop mode operation.
In
Active low Clear to Send inputs for the serial port. Handshake
signal which notifies the UART that the modem is ready to
receive data. The CPU can monitor the status of CTS signal by
reading bit 4 of Modem Status Register (MSR). A CTS signal
state change from low to high after the last MSR read will set
MSR bit 0 to a logic 1. If bit 3 of Interrupt Enable Register is set,
the interrupt is generated when CTS changes state. The CTS
signal has no effect on the transmitter. * Note : Bit 4 of MSR is
the complement of CTS.
In
Active low Data Set Ready inputs for the serial port. Handshake
signal which notifies the UART that the modem is ready to
establish the communication link. The CPU can monitor the status
of DSR signal by reading bit 5 of Modem Status Register (MSR).
A DSR signal state change from low to high after the last MSR
read will set MSR bit 1 to a logic 1. If bit 3 of Interrupt Enable
Register is set, the interrupt is generated when DSR changes state.
* Note : Bit 7 of MSR is the complement of DSR.
In
Active low Data Carrier Detect inputs for the serial port.
Handshake signal which notifies the UART that the carrier signal
detected by the modem. The CPU can monitor the status of DCD
signal by reading bit 7 of Modem Status Register (MSR). A DCD
signal state change from low to high after the last MSR read will
set MSR bit 3 to a 1. If bit 3 of Interrupt Enable Register is set,
the interrupt is generated when DCD changes state. * Note : Bit 7
of MSR is the complement of DCD.