GM82C803CN Datasheet, PDF (35/84 Pages) List of Unclassifed Manufacturers – 2.88 MB FDC/ Dual UARTs with FIFO/PIO(EPP/ ECP)/ IDE Interface/ S-IR/ PnP

GM82C803CN
Operation Register (OR)
This register controls the drive select and motor, enables disk interface outputs the DMA logic, and contains a software
reset bit. It is set to 00H after a hardware reset, and is unaffected by a software reset.
2 Drive Select (Bit 2 of PMR is 0)
D7-6 Should be 0.
D5 Motor on enable : Inverted output MTR1 (pin# : 5) is active.
D4 Motor on enable : Inverted output MTR0 (pin# : 2) is active.
D3 DMA enable : Set to 1 will enable the DRQ, DACK, TC and IRQ pins.
Set to 0 will disable TC, DACK pins and make IRQ, DRQ pins Hi-Z state.
D2 Software Reset : Active low software reset signal.
D1 Should be 0.
D0 Drive Select : If 0 and D4=1, then DS0 (pin# :4) is active.
If 1 and D5=1, then DS1 (pin# :3) is active.
4 Drive Select (Bit 2 of PMR is 1)
Table 4-18. Operation Register for 4 Drive support *Note : Bits 2 and 3 are the same as 2 Drive select.
Bits
7654
Drive Pins
1 0 DS1 DS0 MTR1 MTR0
Encoded Functions
1
00
0
0
1
0
Active Drive & Motor 0
1
01
0
1
1
0
Active Drive & Motor 1
1
10
1
0
1
0
Active Drive & Motor 2
1
11
1
1
1
0
Active Drive & Motor 3
During command or result phase, the main status register must be read by the processor before each byte of
information is written into or read from the data register. Bit 6 and 7 in the main status register must be in a 0 and 1
state, respectively, before each byte of the command word may be written into the FDC. Many of the commands
require multiple bytes and as a result, the main status register must be read prior to each byte transfer to the FDC.
On the other hand, during the result phase, bit 6 and 7 in the main status register must both be 1 before reading
each byte from the data register. (This result of the main status register before each byte transfer to the FDC is
required only in the command and result phase, and not during the execution phase.)
During the execution phase, the main status register need not be read. If the FDC is in the Non-DMA mode, then
the receipt of each data byte ( if FDC is reading data form FDD) is indicated by an interrupt signal on IRQ pin. The
generation of a read signal will reset the interrupt fast enough, then it may poll the main status register and then bit
7 (RQM) functions just like the interrupt signal. If a Write command is in process, then the signal performs the
reset to the interrupt signal.
It is important to note that during the result phase all bytes shown in the command table must be read. The Read
Data Command, for example, has seven bytes of data in the result phase. All seven bytes must be read in order to
successfully complete the Read Data Command. The FDC will not accept a new command until all seven bytes
have been read. Other commands may require fewer bytes to be read during the result phase.
The bytes of data which are sent to the FDC to form the command phase, and are read out of the FDC in the result
phase, must occur in the order shown in the command table. That is, the command code must be sent first and the
other bytes sent in the prescribed sequence. No foreshortening of the command or result phase are allowed. After
the last byte of data in the command phase is sent to the FDC, the execution phase automatically ended and the
FDC is ready for a new command. A command may be aborted by simply sending a Terminal Count signal to TC
pin. This is a convenient means of ensuring that the processor may always get the FDC attention even if the disk
system hangs up in an abnormal manner.
The FDC continues to transfer data until the TC input is active. In Non-DMA host transfers are not the normal
procedure. If the user chooses to do so, the FDC will successfully complete commands, but will always give
abnormal termination error status since TC is qualified by an inactive NACK. In Non-DMA mode, it is necessary
to examine the main status register to determine the cause of the interrupt since it could be a data interrupt or a
command termination interrupt, either normal or abnormal.