GM82C803CN Datasheet, PDF (3/84 Pages) List of Unclassifed Manufacturers – 2.88 MB FDC/ Dual UARTs with FIFO/PIO(EPP/ ECP)/ IDE Interface/ S-IR/ PnP

GM82C803CN
2. Pin Description
PIN NO. PIN BUFFER
NAME TYPE
DESCRIPTION
1) HOST INTERFACE
19, IRQ_A
Out
37-40 IRQ_C
IRQ_D
IRQ_E
IRQ_F
21,52, ^DRQ_A
99 ^DRQ_B
Out
DRQ_C
22,36, DACK_A In
96 DACK_B
DACK_C
27 CS
In
28-34 A0-A10
In
41-43,
97
35 TC
In
44 IOR
In
45 _IOW
In
46 AEN
In
48-51 D0-D7
53-56
57 RESET
In/Out
In
Interrupt Request pin. The interrupt request from the logical
device or IRQIN is output on one of the IRQA-G signals. Refer to
the configuration registers for more information.
If EPP or ECP Mode is enabled, this output is pulsed low, then
released to allow sharing of interrupts.
DMA Request pin. This active high output is the DMA request
for byte transfers of data between the host and the chip. This
signal is cleared on the last byte of the data transfer by the DACK
signal going low (or by IOR going low if DACK was already low
as in demand mode).
DMA Acknowledge pin. This active low input acknowledging the
request for a DMA transfer of data between the host and the chip.
This input enables the DMA read or write internally.
Chip Select pin. When enabled, this active low pin serves as an
input for an external decoder circuit which is used to qualify
address lines above A10.
I/O Address pin. These host address bits determine the I/O
address to be accessed during IOR and IOW cycles. These bits
are latched internally by the leading edge of IOR and IOW. All
internal address decodes use the full A0 to A10 address bits.
Terminal Count pin. This signal indicates to the chip that DMA
data transfer is complete. TC is only accepted when DACK_x is
low. TC is active high.
I/O Read pin. This active low signal is issued by the host
microprocessor to indicate a read operation.
I/O Write pin. This active low signal is issued by the host
microprocessor to indicate a write operation.
Address Enable pin. Active high Address Enable indicates DMA
operations on the host data bus. Used internally to qualify
appropriate address decodes.
Data Bus 0-7. This data bus used by the host microprocessor to
transmit data to and to receive from the chip. These pins are in a
high- impedance state when not in the output mode.
This active high signal resets the chip and must be valid for 500ns
minimum. The affect on the internal registers is described in the
appropriate section. The configuration registers are not affected
by this reset.