GM82C803CN Datasheet, PDF (59/84 Pages) List of Unclassifed Manufacturers – 2.88 MB FDC/ Dual UARTs with FIFO/PIO(EPP/ ECP)/ IDE Interface/ S-IR/ PnP

GM82C803CN
4.3 Serial Ports
Serial ports are completely independent. They perform serial-to-parallel conversion or parallel-to-serial conversion
between a peripheral device or a modem and CPU.
Serial Ports Registers
Internal registers are classified by three types: data, status, and control registers. The data registers are the Receiver
Buffer Register and the Transmitter Holding Register. The status registers are the Line Status Register and the
Modem Status Register. Also the control registers are Divisor Latch LSB and Divisor Latch MSB for baud rate
selection.
The system programmer may be accessed any of the UART registers summarized in Table 4-19 via the CPU. These
registers control UART operations including transmission and reception of data.
Receive Buffer Register (RBR)
This read only register holds the received incoming data byte.
Transmit Holding Register (TUR)
This write only register contains the data to be transmitted.
Line Control Register (LCR)
The system programmer specifies the format of the asynchronous data communication exchanges and sets the Divisor
Latch Access bit via the Line Control Register (LCR). The programmer can also read the contents of the Line Control
Register. The read capability simplifies system programming and eliminates the need for separate storage in system
memory of the line characteristics. Table 4-30 shows the contents of the LCR. Details on each bit follow:
Bit 0 and 1 : These two bits specify the number of bits in each transmitted or received serial character.The encoding
of bit 0 and 1 is as follows.
Table 4-30. The contents of the LCR.
Bit 1 Bit 0
Character Length
0
0
0
1
1
0
1
1
5 Bits
6 Bits
7 Bits
8 Bits
Bit 2 : This bit specifies the number of stop bits transmitted and received in each serial character. If bit 2 is logic 0,
one stop bit is generated in the transmitted data. If bit 2 is logic 1 when a 5-bit word length is selected via bit 0 and 1,
one and a half stop bits are generated. If bit 2 is logic 1 when either a 6-,7-, or 8-b bit word length is selected, two
stop bits are generated. The receiver checks the first stop bit only regardless of the number of stop bit selected.
Bit 3 : This bit is the Parity Enable bit. When bit 3 is logic 1, a parity bit is generated (transmit data) or checked
(receive data) between the last data word bit and stop bit of the serial data. (The parity bit is used to produce an even
or odd number of 1s when the data word bits and the parity bit are summed).