GM82C803CN Datasheet, PDF (28/84 Pages) List of Unclassifed Manufacturers – 2.88 MB FDC/ Dual UARTs with FIFO/PIO(EPP/ ECP)/ IDE Interface/ S-IR/ PnP

GM82C803CN
DMA Mode-Transfers from the FIFO to the Host
(Note : In the reverse mode, the peripheral may not continue to fill the FIFO if it runs out of data to transfer, even if
the chip continues to request more data from the peripheral.)
The ECP activates the Parallel DRQ pin whenever there is data in the FIFO. The DMA controller must respond to
the request by reading data from the FIFO. The ECP will deactivate the Parallel DRQ pin when the FIFO becomes
empty or when the TC becomes true (qualified by Parallel DACK) indicating that no more data is required. Parallel
DRQ goes inactive after Parallel DACK goes active for the last byte of a data transfer (or on the active edge of IOR,
on the last byte, if no edge is present on Parallel DACK. If Parallel DRQ goes inactive due to the FIFO going
empty, then Parallel DRQ is active again as soon as there is one byte in the FIFO. If Parallel DRQ goes inactive
due to the TC, then Parallel DRQ is active again when there is one byte in the FIFO and serviceIntr has been re-
enabled. (Note : A data underrun may occur if Parallel DRQ is not removed in time to prevent an unwanted cycle.)
Interrupt
The interrupts are enabled by serviceIntr in the ECR register.
serviceIntr = 1 Disables the DMA and all of the service interrupts.
serviceIntr = 0 Enables the selected interrupt condition. If the interrupting condition is valid, then the interrupt is
generated immediately when this bit is changed from 1 to 0. This can occur during programmed I/O if the number
of bytes removed or added from/to the FIFO does not cross the threshold.
The interrupt generated is ISA friendly in that it must pulse the interrupt line low, allowing for interrupt sharing.
After a brief pulse low following the interrupt event, the interrupt line is tri-stated so that other interrupts may
assert.
An interrupt is generated when :
1. For DMA transfer : When serviceIntr is 0,dmaEn is 1 and the DMA TC is received.
2. For Programmed I/O :
a. When serviceIntr is 0, dmaEn is 0, direction is 0 and there are writeIntrThreshold or more free bytes in the
FIFO. Also, an interrupt is generated when serviceIntr is cleared to 0 whenever there are writeIntrThreshold or
more free bytes in the FIFO.
b. When serviceIntr is 0, dmaEn is 0, direction is 1 and there are readIntrThreshold or more bytes in the FIFO.
Also, an interrupt is generated when serviceIntr is cleared to 0 whenever there are readIntrThreshold or more bytes
in the FIFO.
3. When ErrIntrEn is 0 and Fault transitions from high to low or when ErrIntEn is set from 1 to 0 and Fault is
asserted.
4. When ackIntrEn is 1 and the Ack signal transitions from low to high.
FIFO Operation
The FIFO threshold is fixed by 8 and supported only in mode 010 and 011. Each data byte is transferred to FIFO by
PIO cycle or DMA. Automatic data transfer is achieved using FIFO.
Programmed I/O MODE or NON-DMA MODE
The ECP or Fast Centronics mode may also be operated using interrupt driven programmed I/O. In Prime3C
WriteIntrThreshold and ReadIntrThreshold are fixed to 8 bytes.
Programmed I/O transfer are to the ecpDFIFO and ecpAFIFO or from ecpDFIFO, or to/from the tFIFO. To use the
PIO transfers, the host first sets up direction and state and sets dmaEn to 0 and serviceIntr to 0. The ECP requests
PIO transfers from the host by activating the PINTR pin. The PIO will empty or fill the FIFO using appropriate
direction and mode.