GM82C803CN Datasheet, PDF (48/84 Pages) List of Unclassifed Manufacturers – 2.88 MB FDC/ Dual UARTs with FIFO/PIO(EPP/ ECP)/ IDE Interface/ S-IR/ PnP

GM82C803CN
If the processor terminates a Read or Write operation in the FDC, then the ID information in the result phase is dependent
upon the state of the MT bit and EOF byte. Table 4-22 shows the values for C,H,R and N, When the processor terminates
the command.
Table 4-22. C,H,R and N values
MT
HD
0
0
0
1
Final Sector Transfer
to Host
Less than EOT
Equal to EOT
Less than EOT
ID Information at Result Phase
C
H
R
N
NC
NC
R+1
NC
C+1
NC
1
NC
NC
NC
R+1
NC
1
Equal to EOT
C+1
NC
R+1
NC
0
0
1
1
1
Less than EOT
Equal to EOT
Less than EOT
Equal to EOT
NC
NC
R+1
NC
NC
1
1
NC
NC
NC
R+1
NC
C+1
0
1
NC
NC (No change) : The same value as the one at the beginning of command execution
Read Deleted data
This command is the same as the read data command except that when the FDC detects a data field (and SK = 0), It will r-
ead all the data in the sector and set the CM flag in status Register 2 to a 1, and then terminate the command, if SK = 1, th-
en the FDC skips the sector with the delta address mark and reads the next sector. Table 4-23 shows SK effect on Read D-
eleted Data command.
Table 4-23. SK Effect on Read Deleted Data command
SK
Data Type
Sector Read
CM bit (in ST2)
0
Normal
Y
1
0
Deleted
Y
0
1
Normal
N
1
1
Deleted
Y
0
Description of result
No Further Sector Read
Normal Termination
Sector Skipped
Normal Termination