GM82C803CN Datasheet, PDF (63/84 Pages) List of Unclassifed Manufacturers – 2.88 MB FDC/ Dual UARTs with FIFO/PIO(EPP/ ECP)/ IDE Interface/ S-IR/ PnP

GM82C803CN
Interrupt Enable Register
This register enables the five types of UART interrupts. Each interrupt can individually activate the interrupt (INT)
output signal. It is possible to totally disable the interrupt system by resetting bits 0 through 3 of the Interrupt Enable
Register (IER). Similarly, setting bits of the IER register to logic 1 enables the selected interrupt(s). Disabling an
interrupt prevents it from being indicated as active in the IIR and from activating the INT output signal. All other
system functions operate in their normal manners, the Line Status and Modem Status Registers. Details on each bit
follow.
Bit 0 : This bit enables the Received Data Available Interrupt (and timeout interrupts in the FIFO mode) when set to
logic 1.
Bit 1 : This bit enables the Transmitter Holding Register Empty Interrupt.
Bit 2 : This bit enables the Receiver Line Status Interrupt when set to logic 1.
Bit 3 : This bit enables the Modem Status Interrupt when set to logic 1.
Bit 4 through 7 : These four bits are always logic 0.
Modem Control Register
This register controls the interface with the Modem or data set (or peripheral device emulating a Modem). The contents
of the Modem Control Register are indicated in Table 4-30 and are described below.
Bit 0 : This bit controls the Data Terminal Ready(DTR) output. When bit 0 is set to logic 1, the DTR output is forced to
logic 0. When bit 0 is reset to logic 0, the DTR output is forced to logic 1.
* Note : The DTR output of the UART may be applied to an EIA inverting line driver (such as the GD75188) to obtain
the proper polarity input at the succeeding Modem or data set.
Bit 1 : This bit controls the Request to Send (RTS) output. Bit 1 affects the RTS output in an identical manner
described above for bit 0.
Bit 2 : This bit controls the output 1(OUT1) signal, which is an auxiliary user-designated output. Bit 2 affects the
OUT1 output in an identical manner described above for bit 0.
Bit 3 : This bit controls the output 2(OUT2) signal, which is an auxiliary user-designated output. Bit 3 affects the
OUT2 output in an identical manner described above for bit 0.
Bit 4 : This bit provides a local loopback feature for diagnostic testing of the UART. When bit 4 is set to logic 1, the
following occurs; the transmitter Serial Output (SOUT) is set to the Marking (logic 1) State; the receiver Serial Input
(SIN) is disconnected; the output of the Transmitter Shift Register is looped back into the Receiver Shift Register input;
the four Modem Control inputs (CTS, DSR, RI, and DCD) are disconnected; the four Modem Control outputs (DTR,
RTS, OUT1, and OUT2) are internally connected to the four Modem Control inputs, and the Modem Control output
pins are forced to their inactive state (high). In the diagnostic mode, transmitted data is immediately received. This
feature allows the processor to verify the transmit- and received-data paths of the UART.
In the diagnostic mode, the receiver and transmitter interrupts are fully operational. Their sources are external to the
part. The Modem Control Interrupts are also operational, but the interrupts sources are now the lower four bits of the
Modem Control Register instead of the four Modem Control inputs. The interrupts are still controlled by the Interrupt
Enable Register.
Bit 5 through 7 : These bits are always set to logic 0.
Modem Status Register
This register provides the current state of the control lines from the Modem (or Peripheral device) to the CPU. In
addition to this current-state information, four bits of the Modem Status Register provide information change. These
bits are set to logic 1 whenever a control input from the Modem changes state. They are reset to logic 0 whenever the
CPU reads the Modem Status Register.
The contents of the MODEM Status Register are indicated in Table 4-30 and described next page.