GM82C803CN Datasheet, PDF (22/84 Pages) List of Unclassifed Manufacturers – 2.88 MB FDC/ Dual UARTs with FIFO/PIO(EPP/ ECP)/ IDE Interface/ S-IR/ PnP

GM82C803CN
EPP DATA PORT 1 REGISTER (base address + 05H)
This register is cleared at initialization by RESET. Refer to EPP DATA PORT 0 for a description of
operation.
EPP DATA PORT 2 REGISTER (base address + 06H)
This register is cleared at initialization by RESET. Refer to EPP DATA PORT 0 for a description of
operation.
EPP DATA PORT 3 REGISTER (base address + 07H)
This register is cleared at initialization by RESET. Refer to EPP DATA PORT 0 for a description of
operation.
TABLE4-3. Parallel Port Pin Out
Connector
Pin No.
SPP , ECP
Mode
Pin
Direction
EPP Mode
Pin
Direction
1
STROBE
I/O
WRITE
I/O
2
PD0
I/O
PD0
I/O
3
PD1
I/O
PD1
I/O
4
PD2
I/O
PD2
I/O
5
PD3
I/O
PD3
I/O
6
PD4
I/O
PD4
I/O
7
PD5
I/O
PD5
I/O
8
PD6
I/O
PD6
I/O
9
PD7
I/O
PD7
I/O
10
ACK
I
ACK
I
11
BUSY
I
WAIT
I
12
PE
I
PE
I
13
SLCT
I
SLCT
I
14
AUTOFD
I/O
DSTRB
I/O
15
ERROR
I
ERROR
I
16
INIT
I/O
INIT
I/O
17
SLCTIN
I/O
ASTRB
I/O
ECP MODE
The ECP mode is another high -speed bi-directional protocol that is implemented in hardware to reduce software and
system overhead.
The ECP mode provided DMA operation, a 16-byte FIFO, bi-directional command/data transfer, command/data FIFO
tag (one per byte), a FIFO threshold interrupt for both directions, FIFO full and full status bits, automatic generation
of strobes by hardware to fill or empty the FIFO and a Run Length Encoding(RLE). The ECP mode is selected in
Function Selection Register(FSR). Once selected, its mode is controlled via the mode field of bit 5,6,7 of ECR Register.
The ECP mode in Prime3C has 10 registers and these registers are shown in table 4.4.
Register definition
The register definition are based on the standard printer address for LPT. All of standard modes are supported in ECP
mode. The port register varies depending on the mode field in the ECR. The table 4.4 lists these dependencies.