GM82C803CN Datasheet, PDF (15/84 Pages) List of Unclassifed Manufacturers – 2.88 MB FDC/ Dual UARTs with FIFO/PIO(EPP/ ECP)/ IDE Interface/ S-IR/ PnP

GM82C803CN
3.1.20 Game chip select Decoding Register (GDR)
Index = D5
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Game Chip Select Configuration
(See Table 3-3)
ADR4
ADR5
ADR6
ADR7
ADR8
ADR9
Bit 1 Bit 0
00
01
10
11
Configuration
GAMECS Disable
ADR[3:0]= 0001b
ADR[3:0]= 0xxxb
ADR[3:0]= xxxxb
(Table 3-3. Game chip select Configuration)
Bit 5 Bit 4
Configuration
00
ADRx Disable
01
1 byte decode, ADR[3:0]= 0001b
10
8 byte decode, ADR[3:0]= 0xxxb
1 1 16 byte decode, ADR[3:0] = xxxxb
(Table 3-4. ADRx Configuration)
3.1.21 Pin 94 Mode Register (PMR)
Index = D6
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
FDC SWAP (0: default, 1: Swap)
FDC DMA nonburst (0: burst default,
4 FDD option
1: non burst )
Reserved
0: internal 2drive decoder default,
1: external 4 drive decoder (* Note)
ADRx Configuration (See Table 3-4)
Pin 94 mode (See Table 3-5)
Bit 7 Bit 6
0x
Configuration
Tri-state
10
ADRX
11
IRQ_B
(Table 3-5. Pin 94 Mode Configuration)
* Note : If you want to use 4 FDD, you require the
external 2 to 4 decoder