GM82C803CN Datasheet, PDF(30/84 Page) List of Unclassifed Manufacturers – 2.88 MB FDC/ Dual UARTs with FIFO/PIO(EPP/ ECP)/ IDE Interface/ S-IR/ PnP

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GM82C803CN Datasheet, PDF (30/84 Pages) List of Unclassifed Manufacturers – 2.88 MB FDC/ Dual UARTs with FIFO/PIO(EPP/ ECP)/ IDE Interface/ S-IR/ PnP

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GM82C803CN

The FDC contains the circuitry and control functions for interfacing a processor to 4 Floppy Disk Drives. The FDC is

capable of supporting either IBM3740 single density format(FM), or IBM system 34 double density format (MFM)

including double sided recording. It simplifies and handles most of the burdens associated with implementing a Flo-

ppy Disk Drive Interface. It supports data rates of 250/300/500 Kb/s and 1Mb/s. This block integrates ; Formatter/

Controller, Data Seperation,Write Precompensation,Data Rate Selection,Clock Generation, Drive interface drivers and

receivers. It has five registers which may be accessed by the main system processor; a Main Status Register(MSR), a

Data rate Selection Register(DSR), a Data Register(DR), a Control Register(CR), and a Operation Register(OR). The

main status register contains the status information of the FDC, and may be accessed at any time. The data rate selec-

tion register is used to program the data rate, amount of write precompensation, power down mode, and software

reset. The data register (actually consists of several registers in a stack with only one register presented to the data bus

at a time) stores data, commands, parameters, and FDD status information. Data bytes are read out of, or written into

the data register in order to program or obtain the results after execution of a command. The status register may only

be read and is used to facilitate the transfer of data between the processor and FDC.

Table 4-7. Register Description and Address

FDC Base

Address

(Hex)

R/W

Reserved

Operation Register (OR)

Reserved

Main Status Register (MSR)

Data Rate Select Register (DSR)

Data Register(FIFO) (DR)

Reserved

Control Register (CR)

Read DSKCHG (D7 only, inverse)

FIFO (Data Register)

The FIFO is used to transfer disk data. It is 16 bytes in size and has programmable threshold values. Data trans-

fers are governed by the RQM and DIO bits in the Main Status Register.

The FIFO has the defaults with 765B compatible mode after a hardware reset. Software resets (Reset via OR or

DSR Register) can also place the FDC into 765B compatible mode if the LOCK bit is set to zero(See the defin-

ition of the LOCK bit in Lock command). This maintains PC/AT hardware compatibility. The default values

can be changed through the Configure command (enable full FIFO operation with threshold control). The adva-

ntage of the FIFO is that it allows the system a larger DMA latency without causing a disk error. Table 4-8

gives several examples of the delays with a FIFO. The data is based upon the following formula.

Threshold#

Data Rate

1.5 = Delay

Table 4-8. FIFO Service Delay

FIFO Threshold

Example

1 byte

2 byte

Maximum Delay to Servicing

at 1 Mbps Data Rate

1.5 = 6.5

1.5 = 14.5

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