GM82C803CN Datasheet, PDF (1/84 Pages) List of Unclassifed Manufacturers – 2.88 MB FDC/ Dual UARTs with FIFO/PIO(EPP/ ECP)/ IDE Interface/ S-IR/ PnP

GM82C803CN
GM82C803CN
2.88 MB FDC/ Dual UARTs with FIFO/
PIO(EPP/ ECP)/ IDE Interface/ S-IR/ PnP
General Description
The GM82C803CN is a single 100-pin PC95
compatible Super I/O chip with a Floppy Disk
Controller with data separator, two UARTs
(GM16C550) and an infrared interface, one Parallel
port (IEEE 1284 Compliant). The GM82C803CN is
optimized for motherboard applications. The
GM82C803CN also includes one game port selection,
IDE interface and an address decoder for on-chip
function. The Floppy Disk Control part provides all
the needed functionality between the host processor
peripheral bus and the cable connector to the Floppy
Disk Driver. It integrates the selection, clock
generation and high current drivers and supports the 4
MB drive as well as the other standard drives. The
UARTs on GM82C803CN are compatible with the
16C550. One UART (COM2) includes Serial Infrared
Interface, complying with IrDA, HPSIR, and ASKIR
streams. The Configuration register is used to allocate
the I/O Base Address IRQ or DMA for each
corresponding function.
Features
„ 100% Hardware compatible to the IBM PC/AT
„ Floppy Disk Controller with 16 bytes FIFO
(default disable)
- Data rates up to 1Mbps
- Perpendicular recording drive support
- Drives up to two FDDs
- 40 mA floppy disk drive interface
- FDD swap
- 48 Base I/O addresses, 7 IRQ and 3 DMA options
Internal Block Diagram
„ Dual UARTs compatible to the GM16C550
- Programmable character lengths (5, 6, 7, 8)
- Even, odd, stick or no parity bit generation and
detection
- Programmable baud rate generator
- High speed baud rate (230 Kbps, 460 Kbps)
support
- Independent transmit/ receiver FIFOs
- MIDI interface
- Modem control
- Infrared -IrDA(HPSIR) and ASK(Amplitude
Shift Keyed)IR
- Optional alternate IR pins
- 96 Base I/O addresses and 7 IRQ options
„ Multi-mode parallel port
- Standard mode
- ECP (IEEE 1284)
- EPP (Version 1.9 : default, Version 1.7)
- 192 Base I/O addresses, 7 IRQ and 3 DMA
options
„ IDE interface (optional)
- 48 Base I/O addresses and 7 IRQ options
„ Game chip selection logic
- 48 Base I/O addresses
„ General Purpose Address Decoder
- 48 Base I/O addresses
„ Power Down support
„ 5 Volt operation
„ 14.318 MHz or 24 MHz clock
„ 100 pin QFP
Data
Address,
Data
and
Control
Data Buffer
14.318 MHz _Game
or 24 MHz _Port
OSC.
PnP,
Configuration
Register
IDE
Interface / IR
IDE Drive Select
or IR Interface
Serial
Interface
Serial /Infrared
Interface
UART 1
(16C550)
UART 2
(16C550)
Power Down
PIO
Logic
FDC
with
FIFO
PData Handshake
FDD Interface