GM82C803CN Datasheet, PDF (19/84 Pages) List of Unclassifed Manufacturers – 2.88 MB FDC/ Dual UARTs with FIFO/PIO(EPP/ ECP)/ IDE Interface/ S-IR/ PnP

GM82C803CN
4. FUNCTIONAL DESCRIPTION
4.1 PARALLEL PORT
The Prime 3C supports the IBM XT/AT Compatible parallel port, the PS/2 type bi-directional parallel port,
the EPP (Enhanced Parallel Port) and the ECP (Extended Capabilities Port) modes. The information on
selecting the mode of operation, changing base address of parallel port, powerdown parallel port and
disabling parallel port are descripted at PRIME3C configuration registers.
IBM XT/AT Compatible Mode
The IBM XT/AT Compatible parallel port is selected in FSR register and supports Centronics style standard
mode. The PRIME3C also supports the optional PS/2 type bi-directional parallel port by setting the bit7 of
PCR register.
The registers used in compatible mode are shown in table 4-1.
REGISTER
ADDRESS
DATA (DTR)
BASE ADDRESS + 00H
STATUS (STR) BASE ADDRESS + 01H
CONTROL (CTR) BASE ADDRESS + 02H ( Table 4-1 Compatible Mode Register Set )
DATA REGISTER (DTR)
This register transfers 8 bit data and is located at an offset of 00H from base address. The reset value is 00H.
In compatible mode, the data written to this register is transmitted to parallel port. The read operation in this
mode causes the data register to present the last data written to it by CPU. In PS/2 style bi-direction mode, a
write operation causes the data to be latched. If the direction bit(the bit5 of CTR) is 0, the latched data is
presented on parallel port. If the direction bit is 1, the data is only latched. When direction bit is 0, a read
operation in this mode causes the data register to present the last data written to port by CPU. When direction
bit is 1 and bi-directional mode, a read operation causes the data on parallel port to be presented on system
data port. The table 4-2 shows these operations.
MODE DIRECTION nIOR
compatible
X
1
compatible
X
0
bi-direction
0
1
bi-direction
1
1
bi-direction
0
0
bi-direction
1
0
nIOW
0
1
0
0
1
1
RESULT
DATA Written to PD[0:7]
DATA Read from the Output Latch
DATA Written to PD[0:7]
DATA Written is Latched
DATA Read from the Output Latch
DATA Read from PD[0:7]
( Table 4-2 Read and Write of Data Register in Compatible and Bi-direction Mode )