GM82C803CN Datasheet, PDF (10/84 Pages) List of Unclassifed Manufacturers – 2.88 MB FDC/ Dual UARTs with FIFO/PIO(EPP/ ECP)/ IDE Interface/ S-IR/ PnP

GM82C803CN
3.1.4 FDC Address Register (FAR)
Index = C3
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0
ADR4
ADR5
ADR6
ADR7
ADR8
ADR9
This register is used to select the base address of the Floppy Disk Controller.
The FDC can be set to 48 locations on 16 byte boundaries from 100H-3F0H.
Upper address decode requirements: CS = ??and A10 = ??are required to access the FDC registers.
A[3:0] are decoded as 0xxxb
3.1.5 IDE Base address Register (IBR)
Index = C4
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0
ADR4
ADR5
ADR6
ADR7
ADR8
ADR9
This register is used to select the base address of the IDE Interface Control Registers (0-7).
This can be set to 48 locations on 16byte boundaries from 100H-3F0H.
Upper address decode requirements: CS = ??and A10 = ??are required to access the IDE registers.
A[3:0] are decoded as 0xxxb
3.1.6 IDE Status address Register (ISR)
Index = C5
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1
0
ADR4
ADR5
ADR6
ADR7
ADR8
ADR9
This register is used to select the base address of the IDE Interface Alternate Status Registers.
This can be set to 48 locations from 106H-3F6H.
Upper address decode requirements: CS = ??and A10 = ??are required to access the IDE registers.
A[3:0] must be 0110b