GM82C803CN Datasheet, PDF (27/84 Pages) List of Unclassifed Manufacturers – 2.88 MB FDC/ Dual UARTs with FIFO/PIO(EPP/ ECP)/ IDE Interface/ S-IR/ PnP

GM82C803CN
Command/Data
ECP mode supports two advanced features to improve the effectiveness of the protocol for some applications. The
features are implemented by allowing the transfer of normal 8-bit data or 8-bit commands.
In the forward direction, normal data is transferred when HostAck is high and an 8-bit command is transferred when
HostAck is low.
The most significant bit of the command indicates whether it is a run-length count (for compression) or a channel
address.
In the reverse direction , normal data is transferred when PeriphAck is high and 8-bit command is transferred when
PeriphAck is low. The most significant bit of command is always zero. Reverse channel addresses are seldom used
and may not be supported in hardware.
Table 4-6. Forward Channel Commands (HostAck Low)
Reverse Channel Commands (PeripAck Low)
D7
D (6:0)
0
Run-Length Count (0-127) (mode 0011 0X00 only)
1
Channel Address (0-127)
Data Compression
Prime3C supports Run Length Encoded (RLE) decompression in hardware and can transfer compressed data to the
peripheral. Run Length Encoded (RLE) compression in hardware is not supported. To transfer compressed data in
ECP mode, the compression count in written to the ecpAfifo and the data byte is written to the ecpDFifo.
Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many
times the next byte is to be repeated. Decompression simply intercepts the RLE byte and repeats the following byte
the specified number of times. When a run-length count is received from a peripheral, the subsequent data byte is
replicated the specified number of times. A run-length count of zero specifies that only one byte of data is repre-
sented by the next data byte, whereas a run-length count of 127 indicates that the next byte should be expanded to
128 bytes. To prevent data expansion, however, run-length counts of zero should be avoided.
Pin Definition
The drivers STROBE, AutoFd, Init and SelectIn are open-collector in mode 000 and are push-pull in all other
modes.
ISA Connections
The interface can never stall causing the host to hang. The width of data transfer is strictly controlled on an I/O
address basis per this specification. All FIFO-DMA transfers are byte wide, byte aligned and end on a byte boundary.
Single byte wide transfers.
DMA Transfer
DMA transfers are always to or from the ecpDfifo, tFifo or CFifo. DMA utilizes the standard PC DMA services. To
use the DMA transfers, the host first sets up the direction and state as in the programmed I/O case. Then it programs
the DMA controller in the host with the desired count and memory address. Lastly it sets dmaEn to 1 and serviceIntr
to 0. The ECP requests DMA transfers from the host by activating the PDRQ pin. The DMA will empty or fill the
FIFO using the appropriate direction and mode. When the terminal count in the DMA controller is reached, an inter-
rupt is generated and serviceIntr is asserted, disabling DMA. In order to prevent possible blocking of refresh requests,
dReq shall not be asserted for more than 32 DMA cycles in a row. The FIFO is enabled directly by asserting PDACK
and addresses need not be valid. PINTR is generated when a TC is received. PDRQ must not be asserted for more
then 32 DMA cycles in a row. After the 32nd cycle, PDRQ must be kept unasserted until PDACK is deasserted for a
minimum of 350nsec. (Note : The dnly way to properly terminate DMA transfers with a TC)
DMA may be disabled in the middle of a transfer by first disabling the host DMA controller. Then setting service Intr
to 1, followed by setting dmaEn to 0, and waiting for the FIFO to become empty or full. Restarting the DMA is
accomplished by enabling DMA in the host, setting dmaEn to 1, followed by setting serviceIntr to 0.